riscv/rocket-chip
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB

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Rimas Avizienis
2011-11-10 11:26:13 -08:00
parent 4bd0263a4a
commit f86d5b1334
9 changed files with 119 additions and 109 deletions
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rocket/src/main/scala/cpu.scala
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@ -7,7 +7,6 @@ import Constants._;
class ioDebug(view: List[String] = null) extends Bundle(view)
{
val error_mode = Bool('output);
val log_control = Bool('output);
val id_valid = Bool('output);
val ex_valid = Bool('output);
val mem_valid = Bool('output);