90 lines
3.2 KiB
Scala
90 lines
3.2 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.amba.axi4
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import Chisel._
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import chisel3.util.Irrevocable
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import freechips.rocketchip.util._
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abstract class AXI4BundleBase(params: AXI4BundleParameters) extends GenericParameterizedBundle(params)
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abstract class AXI4BundleA(params: AXI4BundleParameters) extends AXI4BundleBase(params)
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{
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val id = UInt(width = params.idBits)
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val addr = UInt(width = params.addrBits)
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val len = UInt(width = params.lenBits) // number of beats - 1
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val size = UInt(width = params.sizeBits) // bytes in beat = 2^size
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val burst = UInt(width = params.burstBits)
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val lock = UInt(width = params.lockBits)
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val cache = UInt(width = params.cacheBits)
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val prot = UInt(width = params.protBits)
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val qos = UInt(width = params.qosBits) // 0=no QoS, bigger = higher priority
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val user = if (params.userBits > 0) Some(UInt(width = params.userBits)) else None
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// val region = UInt(width = 4) // optional
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// Number of bytes-1 in this operation
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def bytes1(x:Int=0) = {
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val maxShift = 1 << params.sizeBits
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val tail = UInt((BigInt(1) << maxShift) - 1)
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(Cat(len, tail) << size) >> maxShift
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}
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}
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// A non-standard bundle that can be both AR and AW
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class AXI4BundleARW(params: AXI4BundleParameters) extends AXI4BundleA(params)
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{
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val wen = Bool()
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}
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class AXI4BundleAW(params: AXI4BundleParameters) extends AXI4BundleA(params)
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class AXI4BundleAR(params: AXI4BundleParameters) extends AXI4BundleA(params)
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class AXI4BundleW(params: AXI4BundleParameters) extends AXI4BundleBase(params)
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{
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// id ... removed in AXI4
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val data = UInt(width = params.dataBits)
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val strb = UInt(width = params.dataBits/8)
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val last = Bool()
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}
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class AXI4BundleR(params: AXI4BundleParameters) extends AXI4BundleBase(params)
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{
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val id = UInt(width = params.idBits)
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val data = UInt(width = params.dataBits)
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val resp = UInt(width = params.respBits)
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val user = if (params.userBits > 0) Some(UInt(width = params.userBits)) else None
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val last = Bool()
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}
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class AXI4BundleB(params: AXI4BundleParameters) extends AXI4BundleBase(params)
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{
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val id = UInt(width = params.idBits)
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val resp = UInt(width = params.respBits)
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val user = if (params.userBits > 0) Some(UInt(width = params.userBits)) else None
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}
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class AXI4Bundle(params: AXI4BundleParameters) extends AXI4BundleBase(params)
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{
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val aw = Irrevocable(new AXI4BundleAW(params))
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val w = Irrevocable(new AXI4BundleW (params))
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val b = Irrevocable(new AXI4BundleB (params)).flip
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val ar = Irrevocable(new AXI4BundleAR(params))
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val r = Irrevocable(new AXI4BundleR (params)).flip
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}
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object AXI4Bundle
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{
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def apply(params: AXI4BundleParameters) = new AXI4Bundle(params)
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}
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class AXI4AsyncBundleBase(params: AXI4AsyncBundleParameters) extends GenericParameterizedBundle(params)
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class AXI4AsyncBundle(params: AXI4AsyncBundleParameters) extends AXI4AsyncBundleBase(params)
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{
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val aw = new AsyncBundle(params.depth, new AXI4BundleAW(params.base))
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val w = new AsyncBundle(params.depth, new AXI4BundleW (params.base))
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val b = new AsyncBundle(params.depth, new AXI4BundleB (params.base)).flip
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val ar = new AsyncBundle(params.depth, new AXI4BundleAR(params.base))
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val r = new AsyncBundle(params.depth, new AXI4BundleR (params.base)).flip
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}
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