riscv/rocket-chip
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avoid logical to physical header conversion overflow

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This commit is contained in:
Wei Song 2016-04-22 17:47:34 +01:00
parent f9de99ed40
commit f6e44b1348
1 changed files with 3 additions and 2 deletions
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5
uncore/src/main/scala/interconnect.scala
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@ -107,6 +107,7 @@ class PortedTileLinkCrossbar(
(implicit p: Parameters) (implicit p: Parameters)
extends PortedTileLinkNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) { extends PortedTileLinkNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) {
val n = p(LNEndpoints) val n = p(LNEndpoints)
val phyHdrWidth = log2Up(n)
val count = tlDataBeats val count = tlDataBeats
// Actually instantiate the particular networks required for TileLink // Actually instantiate the particular networks required for TileLink
val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))) val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData())))
@ -134,12 +135,12 @@ class PortedTileLinkCrossbar(
} }
def managerToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = { def managerToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
val out = DefaultToPhysicalShim(n, in) val out = DefaultToPhysicalShim(n, in)
out.bits.header.dst := in.bits.header.dst + UInt(nManagers) out.bits.header.dst := in.bits.header.dst + UInt(nManagers, phyHdrWidth)
out out
} }
def clientToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = { def clientToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = {
val out = DefaultToPhysicalShim(n, in) val out = DefaultToPhysicalShim(n, in)
out.bits.header.src := in.bits.header.src + UInt(nManagers) out.bits.header.src := in.bits.header.src + UInt(nManagers, phyHdrWidth)
out out
} }