From f6e44b13484639e8c406f89f62a6036da93c5546 Mon Sep 17 00:00:00 2001 From: Wei Song Date: Fri, 22 Apr 2016 17:47:34 +0100 Subject: [PATCH] avoid logical to physical header conversion overflow --- uncore/src/main/scala/interconnect.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/uncore/src/main/scala/interconnect.scala b/uncore/src/main/scala/interconnect.scala index 428474ba..2539d461 100644 --- a/uncore/src/main/scala/interconnect.scala +++ b/uncore/src/main/scala/interconnect.scala @@ -107,6 +107,7 @@ class PortedTileLinkCrossbar( (implicit p: Parameters) extends PortedTileLinkNetwork(addrToManagerId, sharerToClientId, clientDepths, managerDepths)(p) { val n = p(LNEndpoints) + val phyHdrWidth = log2Up(n) val count = tlDataBeats // Actually instantiate the particular networks required for TileLink val acqNet = Module(new BasicCrossbar(n, new Acquire, count, Some((a: PhysicalNetworkIO[Acquire]) => a.payload.hasMultibeatData()))) @@ -134,12 +135,12 @@ class PortedTileLinkCrossbar( } def managerToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = { val out = DefaultToPhysicalShim(n, in) - out.bits.header.dst := in.bits.header.dst + UInt(nManagers) + out.bits.header.dst := in.bits.header.dst + UInt(nManagers, phyHdrWidth) out } def clientToCrossbarShim[T <: Data](in: LNIO[T]): PNIO[T] = { val out = DefaultToPhysicalShim(n, in) - out.bits.header.src := in.bits.header.src + UInt(nManagers) + out.bits.header.src := in.bits.header.src + UInt(nManagers, phyHdrWidth) out }