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separate btb response mask from the frontend mask

It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
This commit is contained in:
Christopher Celio 2016-03-26 05:37:26 -07:00
parent 091782ad27
commit f526d380fd
2 changed files with 3 additions and 3 deletions

View File

@ -115,8 +115,8 @@ class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
// - "bridx" is the low-order PC bits of the predicted branch (after // - "bridx" is the low-order PC bits of the predicted branch (after
// shifting off the lowest log(inst_bytes) bits off). // shifting off the lowest log(inst_bytes) bits off).
// - "resp.mask" provides a mask of valid instructions (instructions are // - "mask" provides a mask of valid instructions (instructions are
// masked off by the predicted taken branch). // masked off by the predicted taken branch from the BTB).
class BTBResp(implicit p: Parameters) extends BtbBundle()(p) { class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
val taken = Bool() val taken = Bool()
val mask = Bits(width = fetchWidth) val mask = Bits(width = fetchWidth)

View File

@ -131,7 +131,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
val all_ones = UInt((1 << (fetchWidth+1))-1) val all_ones = UInt((1 << (fetchWidth+1))-1)
val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2) val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2)
io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc) io.cpu.resp.bits.mask := msk_pc
io.cpu.resp.bits.xcpt_if := s2_xcpt_if io.cpu.resp.bits.xcpt_if := s2_xcpt_if
io.cpu.btb_resp.valid := s2_btb_resp_valid io.cpu.btb_resp.valid := s2_btb_resp_valid