From f526d380fdac684469f5fe078ed41eaccc87607d Mon Sep 17 00:00:00 2001 From: Christopher Celio Date: Sat, 26 Mar 2016 05:37:26 -0700 Subject: [PATCH] separate btb response mask from the frontend mask It is now the job of the pipeline to monitor the frontend's valid mask (of instructions) and the BTB's suggested valid mask (based on the prediction it makes). Some processors may want to ignore or override the BTB's prediction and thus can supply their own instruction mask. --- rocket/src/main/scala/btb.scala | 4 ++-- rocket/src/main/scala/frontend.scala | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala index a86357e6..0cb33e7e 100644 --- a/rocket/src/main/scala/btb.scala +++ b/rocket/src/main/scala/btb.scala @@ -115,8 +115,8 @@ class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) { // - "bridx" is the low-order PC bits of the predicted branch (after // shifting off the lowest log(inst_bytes) bits off). -// - "resp.mask" provides a mask of valid instructions (instructions are -// masked off by the predicted taken branch). +// - "mask" provides a mask of valid instructions (instructions are +// masked off by the predicted taken branch from the BTB). class BTBResp(implicit p: Parameters) extends BtbBundle()(p) { val taken = Bool() val mask = Bits(width = fetchWidth) diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala index 96e7c2ec..e98df9d3 100644 --- a/rocket/src/main/scala/frontend.scala +++ b/rocket/src/main/scala/frontend.scala @@ -131,7 +131,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa val all_ones = UInt((1 << (fetchWidth+1))-1) val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2) - io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc) + io.cpu.resp.bits.mask := msk_pc io.cpu.resp.bits.xcpt_if := s2_xcpt_if io.cpu.btb_resp.valid := s2_btb_resp_valid