riscv/rocket-chip
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separate btb response mask from the frontend mask

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It is now the job of the pipeline to monitor the frontend's valid mask (of
instructions) and the BTB's suggested valid mask (based on the prediction it
makes). Some processors may want to ignore or override the BTB's prediction and
thus can supply their own instruction mask.
This commit is contained in:
Christopher Celio
2016-03-26 05:37:26 -07:00
parent 091782ad27
commit f526d380fd
2 changed files with 3 additions and 3 deletions
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2
rocket/src/main/scala/frontend.scala
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@ -131,7 +131,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
val all_ones = UInt((1 << (fetchWidth+1))-1)
val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2)
io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc)
io.cpu.resp.bits.mask := msk_pc
io.cpu.resp.bits.xcpt_if := s2_xcpt_if
io.cpu.btb_resp.valid := s2_btb_resp_valid