riscv/rocket-chip
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Merge pull request #1177 from freechipsproject/dont-touch-2

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Make more use of chisel3.experimental.DontTouch
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Henry Cook
2018-01-09 15:13:55 -08:00
committed by GitHub
parent c152962642 15c54b1c5a
commit f5211765e9
7 changed files with 26 additions and 15 deletions
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2
src/main/scala/rocket/HellaCache.scala
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@ -4,6 +4,7 @@
package freechips.rocketchip.rocket
import Chisel._
import chisel3.experimental.dontTouch
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._
@ -184,6 +185,7 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
implicit val edge = outer.node.edges.out(0)
val (tl_out, _) = outer.node.out(0)
val io = IO(new HellaCacheBundle(outer))
dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals
private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allUncacheable)
fifoManagers.foreach { m =>