Merge pull request #1177 from freechipsproject/dont-touch-2

Make more use of chisel3.experimental.DontTouch

src/main/scala/coreplex/HasTiles.scala

@@ -3,6 +3,7 @@
 package freechips.rocketchip.coreplex
 
 import Chisel._
+import chisel3.experimental.dontTouch
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
@@ -37,9 +38,9 @@ trait HasTilesModuleImp extends LazyModuleImp
     vectors.head.getWidth
   }
 
-  val tile_inputs = Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial {
+  val tile_inputs = dontTouch(Wire(Vec(outer.nTiles, new ClockedTileInputs()(p.alterPartial {
     case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
-  })))
+  })))) // dontTouch keeps constant prop from sucking these signals into the tile
 
   // Unconditionally wire up the non-diplomatic tile inputs
   outer.tiles.map(_.module).zip(tile_inputs).foreach { case(tile, wire) =>

src/main/scala/coreplex/RocketCoreplex.scala

@@ -118,18 +118,14 @@ trait HasRocketTiles extends HasTiles
     def tileSlaveBuffering: TLInwardNode = rocket {
       val slaveBuffer  = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
       crossing.crossingType match {
-        case _: SynchronousCrossing  => rocket.slaveNode // requirement already checked
-        case _: AsynchronousCrossing => rocket.slaveNode
-        case _: RationalCrossing =>
-          if (tp.boundaryBuffers) {
-            DisableMonitors { implicit p => rocket.slaveNode :*= slaveBuffer.node }
-          } else {
-            rocket.slaveNode
-          }
+        case RationalCrossing(_) if (tp.boundaryBuffers) => rocket.slaveNode :*= slaveBuffer.node
+        case _ => rocket.slaveNode
       }
     }
 
-    pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)(tileSlaveBuffering :*= rocket.crossTLIn) }
+    pbus.toTile(tp.name) { implicit p => crossing.slave.adapt(this)( DisableMonitors { implicit p =>
+      tileSlaveBuffering :*= rocket.crossTLIn
+    })}
 
     // Handle all the different types of interrupts crossing to or from the tile:
     // 1. Debug interrupt is definitely asynchronous in all cases.
@@ -151,7 +147,7 @@ trait HasRocketTiles extends HasTiles
     if (tp.core.useVM) periphIntNode := plic.intnode // seip
 
     // 3. local interrupts  never cross 
-    // this.intInwardNode is wired up externally     // lip
+    // rocket.intInwardNode is wired up externally     // lip
 
     // 4. conditional crossing from core to PLIC
     FlipRendering { implicit p =>