riscv/rocket-chip
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subsytem: change front bus buffer defaults (#1300)

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Henry Cook 2018-03-21 11:56:22 -07:00 committed by GitHub
parent 894960678c
commit f48c2767d7
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2 changed files with 4 additions and 4 deletions
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6
src/main/scala/subsystem/FrontBus.scala
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@ -12,7 +12,7 @@ case class FrontBusParams(
beatBytes: Int, beatBytes: Int,
blockBytes: Int, blockBytes: Int,
sbusCrossing: SubsystemClockCrossing = SynchronousCrossing(), sbusCrossing: SubsystemClockCrossing = SynchronousCrossing(),
sbusBuffer: BufferParams = BufferParams.default) extends HasTLBusParams sbusBuffer: BufferParams = BufferParams.none) extends HasTLBusParams
case object FrontBusKey extends Field[FrontBusParams] case object FrontBusKey extends Field[FrontBusParams]
@ -23,7 +23,7 @@ class FrontBus(params: FrontBusParams)
val crossing = params.sbusCrossing val crossing = params.sbusCrossing
def fromPort[D,U,E,B <: Data] def fromPort[D,U,E,B <: Data]
(name: Option[String] = None, buffers: Int = 1) (name: Option[String] = None, buffers: Int = 0)
(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
from("port" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } from("port" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen }
@ -34,7 +34,7 @@ class FrontBus(params: FrontBusParams)
} }
def fromMaster[D,U,E,B <: Data] def fromMaster[D,U,E,B <: Data]
(name: Option[String] = None, buffers: Int = 1) (name: Option[String] = None, buffers: Int = 0)
(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
from("master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } from("master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen }

2
src/main/scala/subsystem/Ports.scala
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@ -130,7 +130,7 @@ trait HasSlaveAXI4Port { this: BaseSubsystem =>
id = IdRange(0, 1 << params.idBits)))))) id = IdRange(0, 1 << params.idBits))))))
private val fifoBits = 1 private val fifoBits = 1
sbus.fromPort(Some(portName)) { fbus.fromPort(Some(portName), buffers = 1) {
(TLWidthWidget(params.beatBytes) (TLWidthWidget(params.beatBytes)
:= AXI4ToTL() := AXI4ToTL()
:= AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1))) := AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))