From f48c2767d7a33202263009e5d43ea1f5a617ad46 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 21 Mar 2018 11:56:22 -0700 Subject: [PATCH] subsytem: change front bus buffer defaults (#1300) --- src/main/scala/subsystem/FrontBus.scala | 6 +++--- src/main/scala/subsystem/Ports.scala | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/subsystem/FrontBus.scala b/src/main/scala/subsystem/FrontBus.scala index 2539ccdc..d6803f51 100644 --- a/src/main/scala/subsystem/FrontBus.scala +++ b/src/main/scala/subsystem/FrontBus.scala @@ -12,7 +12,7 @@ case class FrontBusParams( beatBytes: Int, blockBytes: Int, sbusCrossing: SubsystemClockCrossing = SynchronousCrossing(), - sbusBuffer: BufferParams = BufferParams.default) extends HasTLBusParams + sbusBuffer: BufferParams = BufferParams.none) extends HasTLBusParams case object FrontBusKey extends Field[FrontBusParams] @@ -23,7 +23,7 @@ class FrontBus(params: FrontBusParams) val crossing = params.sbusCrossing def fromPort[D,U,E,B <: Data] - (name: Option[String] = None, buffers: Int = 1) + (name: Option[String] = None, buffers: Int = 0) (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { from("port" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } @@ -34,7 +34,7 @@ class FrontBus(params: FrontBusParams) } def fromMaster[D,U,E,B <: Data] - (name: Option[String] = None, buffers: Int = 1) + (name: Option[String] = None, buffers: Int = 0) (gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] = TLIdentity.gen): InwardNodeHandle[D,U,E,B] = { from("master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen } diff --git a/src/main/scala/subsystem/Ports.scala b/src/main/scala/subsystem/Ports.scala index 40d38a34..2b4471dc 100644 --- a/src/main/scala/subsystem/Ports.scala +++ b/src/main/scala/subsystem/Ports.scala @@ -130,7 +130,7 @@ trait HasSlaveAXI4Port { this: BaseSubsystem => id = IdRange(0, 1 << params.idBits)))))) private val fifoBits = 1 - sbus.fromPort(Some(portName)) { + fbus.fromPort(Some(portName), buffers = 1) { (TLWidthWidget(params.beatBytes) := AXI4ToTL() := AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))