51 lines
1.7 KiB
Scala
51 lines
1.7 KiB
Scala
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.subsystem
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import Chisel._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case class FrontBusParams(
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beatBytes: Int,
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blockBytes: Int,
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sbusCrossing: SubsystemClockCrossing = SynchronousCrossing(),
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sbusBuffer: BufferParams = BufferParams.none) extends HasTLBusParams
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case object FrontBusKey extends Field[FrontBusParams]
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class FrontBus(params: FrontBusParams)
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(implicit p: Parameters) extends TLBusWrapper(params, "front_bus")
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with HasTLXbarPhy
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with HasCrossing {
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val crossing = params.sbusCrossing
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def fromPort[D,U,E,B <: Data]
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(name: Option[String] = None, buffers: Int = 0)
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(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
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TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
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from("port" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen }
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}
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def fromMasterNode(name: Option[String] = None, buffers: Int = 1)(gen: TLOutwardNode) {
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from("master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen }
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}
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def fromMaster[D,U,E,B <: Data]
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(name: Option[String] = None, buffers: Int = 0)
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(gen: => NodeHandle[D,U,E,B,TLClientPortParameters,TLManagerPortParameters,TLEdgeOut,TLBundle] =
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TLIdentity.gen): InwardNodeHandle[D,U,E,B] = {
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from("master" named name) { fixFrom(TLFIFOFixer.all, buffers) :=* gen }
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}
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def fromCoherentChip(gen: => TLNode): TLInwardNode = {
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from("coherent_subsystem") { inwardNode :=* gen }
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}
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def toSystemBus(gen: => TLInwardNode) {
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to("sbus") { gen :=* TLBuffer(params.sbusBuffer) :=* outwardNode }
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}
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}
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