riscv/rocket-chip
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Remove uarch counters

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These will be replaced with the indirect TDR scheme used by breakpoints.
This commit is contained in:
Andrew Waterman
2016-07-06 01:37:39 -07:00
parent 25fdabdd59
commit f3e22984d5
2 changed files with 0 additions and 3 deletions
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2
rocket/src/main/scala/csr.scala
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@@ -121,7 +121,6 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
val evec = UInt(OUTPUT, vaddrBitsExtended) val evec = UInt(OUTPUT, vaddrBitsExtended)
val exception = Bool(INPUT) val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+retireWidth)) val retire = UInt(INPUT, log2Up(1+retireWidth))
val uarch_counters = Vec(16, UInt(INPUT, log2Up(1+retireWidth)))
val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen)) val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
val cause = UInt(INPUT, xLen) val cause = UInt(INPUT, xLen)
val pc = UInt(INPUT, vaddrBitsExtended) val pc = UInt(INPUT, vaddrBitsExtended)
@@ -207,7 +206,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val reg_sptbr = Reg(new PTBR) val reg_sptbr = Reg(new PTBR)
val reg_wfi = Reg(init=Bool(false)) val reg_wfi = Reg(init=Bool(false))
val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
val reg_fflags = Reg(UInt(width = 5)) val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3)) val reg_frm = Reg(UInt(width = 3))

1
rocket/src/main/scala/rocket.scala
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@@ -474,7 +474,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
csr.io.rocc.interrupt <> io.rocc.interrupt csr.io.rocc.interrupt <> io.rocc.interrupt
csr.io.pc := wb_reg_pc csr.io.pc := wb_reg_pc
csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc) csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc)
csr.io.uarch_counters.foreach(_ := Bool(false))
io.ptw.ptbr := csr.io.ptbr io.ptw.ptbr := csr.io.ptbr
io.ptw.invalidate := csr.io.fatc io.ptw.invalidate := csr.io.fatc
io.ptw.status := csr.io.status io.ptw.status := csr.io.status