diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index 039a07f2..c36bdfed 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -121,7 +121,6 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle {
   val evec = UInt(OUTPUT, vaddrBitsExtended)
   val exception = Bool(INPUT)
   val retire = UInt(INPUT, log2Up(1+retireWidth))
-  val uarch_counters = Vec(16, UInt(INPUT, log2Up(1+retireWidth)))
   val custom_mrw_csrs = Vec(nCustomMrwCsrs, UInt(INPUT, xLen))
   val cause = UInt(INPUT, xLen)
   val pc = UInt(INPUT, vaddrBitsExtended)
@@ -207,7 +206,6 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
   val reg_sptbr = Reg(new PTBR)
   val reg_wfi = Reg(init=Bool(false))
 
-  val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
   val reg_fflags = Reg(UInt(width = 5))
   val reg_frm = Reg(UInt(width = 3))
 
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index a94bdfa4..7425f724 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -474,7 +474,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   csr.io.rocc.interrupt <> io.rocc.interrupt
   csr.io.pc := wb_reg_pc
   csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc)
-  csr.io.uarch_counters.foreach(_ := Bool(false))
   io.ptw.ptbr := csr.io.ptbr
   io.ptw.invalidate := csr.io.fatc
   io.ptw.status := csr.io.status