riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Remove uarch counters

Browse Source 
These will be replaced with the indirect TDR scheme used by breakpoints.
This commit is contained in:
Andrew Waterman
2016-07-06 01:37:39 -07:00
parent 25fdabdd59
commit f3e22984d5
2 changed files with 0 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
rocket/src/main/scala/rocket.scala
View File

@ -474,7 +474,6 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
csr.io.rocc.interrupt <> io.rocc.interrupt
csr.io.pc := wb_reg_pc
csr.io.badaddr := Mux(wb_reg_mem_xcpt, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), wb_reg_pc)
csr.io.uarch_counters.foreach(_ := Bool(false))
io.ptw.ptbr := csr.io.ptbr
io.ptw.invalidate := csr.io.fatc
io.ptw.status := csr.io.status