74 lines
3.0 KiB
Scala
74 lines
3.0 KiB
Scala
// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
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def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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}
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def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo))
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(Some(monitor), () => {
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bi <> bo
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monitor.module.io.in := TLBundleSnoop(bo)
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})
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}
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override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLClientPortParameters =
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pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters =
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pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
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}
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case class TLIdentityNode() extends IdentityNode(TLImp)
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case class TLOutputNode() extends OutputNode(TLImp)
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case class TLInputNode() extends InputNode(TLImp)
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case class TLClientNode(params: TLClientParameters, numPorts: Range.Inclusive = 1 to 1)
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extends SourceNode(TLImp)(TLClientPortParameters(Seq(params)), numPorts)
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case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1, minLatency: Int = 0)
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extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes, minLatency), numPorts)
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case class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1)
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extends InteriorNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)
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/** Synthesizeable unit tests */
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import unittest._
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class TLInputNodeTest extends UnitTest(500000) {
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class Acceptor extends LazyModule {
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val node = TLInputNode()
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val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
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tlram.node := node
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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}
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}
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val fuzzer = LazyModule(new TLFuzzer(5000))
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LazyModule(new Acceptor).node := TLFragmenter(4, 64)(fuzzer.node)
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io.finished := Module(fuzzer.module).io.finished
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}
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