Chisel3 compatibility changes
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@ -4,7 +4,6 @@ package rocket
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import Chisel._
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import Chisel._
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import Util._
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import Util._
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import Node._
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import uncore._
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import uncore._
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case object NBTBEntries extends Field[Int]
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case object NBTBEntries extends Field[Int]
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@ -5,7 +5,6 @@ package rocket
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import Chisel._
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import Chisel._
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import Util._
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import Util._
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import Instructions._
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import Instructions._
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import Node._
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import uncore._
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import uncore._
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import scala.math._
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import scala.math._
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@ -421,7 +420,7 @@ class CSRFile extends CoreModule
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val new_sstatus = new SStatus().fromBits(wdata)
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val new_sstatus = new SStatus().fromBits(wdata)
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reg_mstatus.ie := new_sstatus.ie
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reg_mstatus.ie := new_sstatus.ie
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reg_mstatus.ie1 := new_sstatus.pie
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reg_mstatus.ie1 := new_sstatus.pie
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reg_mstatus.prv1 := Mux(new_sstatus.ps, PRV_S, PRV_U)
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reg_mstatus.prv1 := Mux[UInt](new_sstatus.ps, PRV_S, PRV_U)
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reg_mstatus.mprv := new_sstatus.mprv
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reg_mstatus.mprv := new_sstatus.mprv
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reg_mstatus.fs := new_sstatus.fs // even without an FPU
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reg_mstatus.fs := new_sstatus.fs // even without an FPU
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if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs
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if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs
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@ -3,7 +3,6 @@
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package rocket
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package rocket
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import Chisel._
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import Chisel._
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import Node._
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object DecodeLogic
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object DecodeLogic
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{
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{
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@ -3,7 +3,6 @@
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package rocket
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package rocket
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import Chisel._
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import Chisel._
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import Node._
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import Instructions._
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import Instructions._
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object ALU
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object ALU
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@ -3,7 +3,6 @@
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package rocket
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package rocket
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import Chisel._
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import Chisel._
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import Node._
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/* Automatically generated by parse-opcodes */
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/* Automatically generated by parse-opcodes */
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object Instructions {
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object Instructions {
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@ -3,7 +3,6 @@
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package rocket
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package rocket
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import Chisel._
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import Chisel._
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import Node._
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import uncore._
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import uncore._
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import Util._
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import Util._
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