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Chisel3 compatibility changes

This commit is contained in:
Andrew Waterman 2015-07-27 12:42:20 -07:00
parent ae73e3a997
commit f2dcc40e67
6 changed files with 1 additions and 7 deletions

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@ -4,7 +4,6 @@ package rocket
import Chisel._ import Chisel._
import Util._ import Util._
import Node._
import uncore._ import uncore._
case object NBTBEntries extends Field[Int] case object NBTBEntries extends Field[Int]

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@ -5,7 +5,6 @@ package rocket
import Chisel._ import Chisel._
import Util._ import Util._
import Instructions._ import Instructions._
import Node._
import uncore._ import uncore._
import scala.math._ import scala.math._
@ -421,7 +420,7 @@ class CSRFile extends CoreModule
val new_sstatus = new SStatus().fromBits(wdata) val new_sstatus = new SStatus().fromBits(wdata)
reg_mstatus.ie := new_sstatus.ie reg_mstatus.ie := new_sstatus.ie
reg_mstatus.ie1 := new_sstatus.pie reg_mstatus.ie1 := new_sstatus.pie
reg_mstatus.prv1 := Mux(new_sstatus.ps, PRV_S, PRV_U) reg_mstatus.prv1 := Mux[UInt](new_sstatus.ps, PRV_S, PRV_U)
reg_mstatus.mprv := new_sstatus.mprv reg_mstatus.mprv := new_sstatus.mprv
reg_mstatus.fs := new_sstatus.fs // even without an FPU reg_mstatus.fs := new_sstatus.fs // even without an FPU
if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs if (!params(BuildRoCC).isEmpty) reg_mstatus.xs := new_sstatus.xs

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@ -3,7 +3,6 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._
object DecodeLogic object DecodeLogic
{ {

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@ -3,7 +3,6 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._
import Instructions._ import Instructions._
object ALU object ALU

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@ -3,7 +3,6 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._
/* Automatically generated by parse-opcodes */ /* Automatically generated by parse-opcodes */
object Instructions { object Instructions {

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@ -3,7 +3,6 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._
import uncore._ import uncore._
import Util._ import Util._