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Merge pull request #403 from ucb-bar/fix-incisive-warning

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Fix Verilog compile warning from Cadence Incisive
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Scott Johnson 2016-10-18 10:48:32 -07:00 committed by GitHub
commit f069052969
1 changed files with 1 additions and 1 deletions
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vsrc/TestDriver.v
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@ -22,7 +22,7 @@ module TestDriver;
int unsigned rand_value; int unsigned rand_value;
initial initial
begin begin
$value$plusargs("max-cycles=%d", max_cycles); void'($value$plusargs("max-cycles=%d", max_cycles));
verbose = $test$plusargs("verbose"); verbose = $test$plusargs("verbose");
// do not delete the line below. // do not delete the line below.