From dc4c375c7f7467898e3d38e945c32f0296390c3c Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Mon, 17 Oct 2016 15:44:24 -0700 Subject: [PATCH] Silence Verilog compile warning from Cadence Incisive --- vsrc/TestDriver.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v index c0b4d50e..554480d2 100644 --- a/vsrc/TestDriver.v +++ b/vsrc/TestDriver.v @@ -22,7 +22,7 @@ module TestDriver; int unsigned rand_value; initial begin - $value$plusargs("max-cycles=%d", max_cycles); + void'($value$plusargs("max-cycles=%d", max_cycles)); verbose = $test$plusargs("verbose"); // do not delete the line below.