riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into hwacha-port

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This commit is contained in:
Quan Nguyen 2014-02-06 00:21:28 -08:00
commit f021213b1d
3 changed files with 39 additions and 1 deletions
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1
rocket/src/main/scala/dpath.scala
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@ -193,6 +193,7 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
pcr.io.rocc <> io.rocc pcr.io.rocc <> io.rocc
pcr.io.pc := wb_reg_pc pcr.io.pc := wb_reg_pc
io.ctrl.csr_replay := pcr.io.replay io.ctrl.csr_replay := pcr.io.replay
pcr.io.uarch_counters.foreach(_ := Bool(false))
io.ptw.ptbr := pcr.io.ptbr io.ptw.ptbr := pcr.io.ptbr
io.ptw.invalidate := pcr.io.fatc io.ptw.invalidate := pcr.io.fatc

7
rocket/src/main/scala/dpath_util.scala
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@ -99,6 +99,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val evec = UInt(OUTPUT, VADDR_BITS+1) val evec = UInt(OUTPUT, VADDR_BITS+1)
val exception = Bool(INPUT) val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+conf.retireWidth)) val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth)))
val cause = UInt(INPUT, conf.xprlen) val cause = UInt(INPUT, conf.xprlen)
val badvaddr_wen = Bool(INPUT) val badvaddr_wen = Bool(INPUT)
val pc = UInt(INPUT, VADDR_BITS+1) val pc = UInt(INPUT, VADDR_BITS+1)
@ -125,6 +126,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val reg_status = Reg(new Status) // reset down below val reg_status = Reg(new Status) // reset down below
val reg_time = WideCounter(conf.xprlen) val reg_time = WideCounter(conf.xprlen)
val reg_instret = WideCounter(conf.xprlen, io.retire) val reg_instret = WideCounter(conf.xprlen, io.retire)
val reg_uarch_counters = io.uarch_counters.map(WideCounter(conf.xprlen, _))
val reg_fflags = Reg(UInt(width = 5)) val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3)) val reg_frm = Reg(UInt(width = 3))
@ -210,7 +212,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val read_impl = Bits(2) val read_impl = Bits(2)
val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
val read_mapping = Map[Int,Bits]( val read_mapping = collection.mutable.Map[Int,Bits](
CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)), CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)),
CSRs.frm -> (if (conf.fpu) reg_frm else UInt(0)), CSRs.frm -> (if (conf.fpu) reg_frm else UInt(0)),
CSRs.fcsr -> (if (conf.fpu) Cat(reg_frm, reg_fflags) else UInt(0)), CSRs.fcsr -> (if (conf.fpu) Cat(reg_frm, reg_fflags) else UInt(0)),
@ -237,6 +239,9 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
CSRs.tohost -> reg_tohost, CSRs.tohost -> reg_tohost,
CSRs.fromhost -> reg_fromhost) CSRs.fromhost -> reg_fromhost)
for (i <- 0 until reg_uarch_counters.size)
read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
io.fcsr_rm := reg_frm io.fcsr_rm := reg_frm

32
rocket/src/main/scala/instructions.scala
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@ -219,6 +219,22 @@ object CSRs {
val fflags = 0x1 val fflags = 0x1
val frm = 0x2 val frm = 0x2
val fcsr = 0x3 val fcsr = 0x3
val uarch0 = 0x80
val uarch1 = 0x81
val uarch2 = 0x82
val uarch3 = 0x83
val uarch4 = 0x84
val uarch5 = 0x85
val uarch6 = 0x86
val uarch7 = 0x87
val uarch8 = 0x88
val uarch9 = 0x89
val uarch10 = 0x8a
val uarch11 = 0x8b
val uarch12 = 0x8c
val uarch13 = 0x8d
val uarch14 = 0x8e
val uarch15 = 0x8f
val sup0 = 0x500 val sup0 = 0x500
val sup1 = 0x501 val sup1 = 0x501
val epc = 0x502 val epc = 0x502
@ -247,6 +263,22 @@ object CSRs {
res += fflags res += fflags
res += frm res += frm
res += fcsr res += fcsr
res += uarch0
res += uarch1
res += uarch2
res += uarch3
res += uarch4
res += uarch5
res += uarch6
res += uarch7
res += uarch8
res += uarch9
res += uarch10
res += uarch11
res += uarch12
res += uarch13
res += uarch14
res += uarch15
res += sup0 res += sup0
res += sup1 res += sup1
res += epc res += epc