tilelink2: refactor TLNodes into a seperate file

uncore/src/main/scala/tilelink2/Nodes.scala

@@ -20,36 +20,36 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Bundle]
 }
 
 class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
-  private val clientFn:  Option[Seq[PO] => PO],
+  private val oFn: Option[Seq[PO] => PO],
-  private val managerFn: Option[Seq[PI] => PI],
+  private val iFn: Option[Seq[PI] => PI],
-  private val numClientPorts:  Range.Inclusive,
+  private val numPO: Range.Inclusive,
-  private val numManagerPorts: Range.Inclusive)
+  private val numPI: Range.Inclusive)
 {
   // At least 0 ports must be supported
-  require (!numClientPorts.isEmpty)
+  require (!numPO.isEmpty)
-  require (!numManagerPorts.isEmpty)
+  require (!numPI.isEmpty)
-  require (numClientPorts.start >= 0)
+  require (numPO.start >= 0)
-  require (numManagerPorts.start >= 0)
+  require (numPI.start >= 0)
 
-  val noClients  = numClientPorts.size  == 1 && numClientPorts.contains(0)
+  val noOs = numPO.size == 1 && numPO.contains(0)
-  val noManagers = numManagerPorts.size == 1 && numManagerPorts.contains(0)
+  val noIs = numPI.size == 1 && numPI.contains(0)
 
-  require (noClients  || clientFn.isDefined)
+  require (noOs || oFn.isDefined)
-  require (noManagers || managerFn.isDefined)
+  require (noIs || iFn.isDefined)
 
-  private val accClientPorts  = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
+  private val accPO = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
-  private val accManagerPorts = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
+  private val accPI = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
-  private var clientRealized  = false
+  private var oRealized  = false
-  private var managerRealized = false
+  private var iRealized = false
 
-  private lazy val clientPorts  = { clientRealized  = true; require (numClientPorts.contains(accClientPorts.size));   accClientPorts.result() }
+  private lazy val oPorts = { oRealized = true; require (numPO.contains(accPO.size)); accPO.result() }
-  private lazy val managerPorts = { managerRealized = true; require (numManagerPorts.contains(accManagerPorts.size)); accManagerPorts.result() }
+  private lazy val iPorts = { iRealized = true; require (numPI.contains(accPI.size)); accPI.result() }
-  private lazy val clientParams  : Option[PO] = clientFn.map(_(managerPorts.map(_.clientParams.get)))
+  private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
-  private lazy val managerParams : Option[PI] = managerFn.map(_(clientPorts.map(_.managerParams.get)))
+  private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))
+
+  lazy val edgesOut = oPorts.map { n => imp.edgeO(oParams.get, n.iParams.get) }
+  lazy val edgesIn  = iPorts.map { n => imp.edgeI(n.oParams.get, iParams.get) }
 
-  lazy val edgesOut = clientPorts.map  { n => imp.edgeO(clientParams.get, n.managerParams.get) }
-  lazy val edgesIn  = managerPorts.map { n => imp.edgeI(n.clientParams.get, managerParams.get) }
-  
   lazy val bundleOut = imp.bundleO(edgesOut)
   lazy val bundleIn  = imp.bundleI(edgesIn)
 
@@ -58,103 +58,50 @@ class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
 
   // source.edge(sink)
   protected[tilelink2] def edge(x: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
-    require (!noClients)
+    require (!noOs)
-    require (!clientRealized)
+    require (!oRealized)
-    require (!x.noManagers)
+    require (!x.noIs)
-    require (!x.managerRealized)
+    require (!x.iRealized)
-    val i = x.accManagerPorts.size
+    val i = x.accPI.size
-    val o = accClientPorts.size
+    val o = accPO.size
-    accClientPorts += x
+    accPO += x
-    x.accManagerPorts += this
+    x.accPI += this
     () => {
       imp.connect(connectOut(o), edgesOut(o), x.connectIn(i), x.edgesIn(i))
     }
   }
 }
 
-class TLClientNode(
+class OutputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
-  params: TLClientParameters,
+  extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
-  numPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
-    clientFn  = Some {case Seq() => TLClientPortParameters(Seq(params))},
-    managerFn = None,
-    numClientPorts  = numPorts,
-    numManagerPorts = 0 to 0)
-{
-  require(numPorts.end >= 1)
-}
-
-object TLClientNode
-{
-  def apply(
-    params: TLClientParameters,
-    numPorts: Range.Inclusive = 1 to 1) = new TLClientNode(params, numPorts)
-}
-
-class TLManagerNode(
-  beatBytes: Int,
-  params: TLManagerParameters, 
-  numPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
-    clientFn  = None,
-    managerFn = Some {case Seq() => TLManagerPortParameters(Seq(params), beatBytes)},
-    numClientPorts  = 0 to 0,
-    numManagerPorts = numPorts)
-{
-  require(numPorts.end >= 1)
-}
-
-object TLManagerNode
-{
-  def apply(
-    beatBytes: Int,
-    params: TLManagerParameters,
-    numPorts: Range.Inclusive = 1 to 1) = new TLManagerNode(beatBytes, params, numPorts)
-}
-
-class TLAdapterNode(
-  clientFn:        Seq[TLClientPortParameters]  => TLClientPortParameters,
-  managerFn:       Seq[TLManagerPortParameters] => TLManagerPortParameters,
-  numClientPorts:  Range.Inclusive = 1 to 1,
-  numManagerPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
-    clientFn  = Some(clientFn),
-    managerFn = Some(managerFn),
-    numClientPorts  = numClientPorts,
-    numManagerPorts = numManagerPorts)
-
-object TLAdapterNode
-{
-  def apply(
-    clientFn:        Seq[TLClientPortParameters]  => TLClientPortParameters,
-    managerFn:       Seq[TLManagerPortParameters] => TLManagerPortParameters,
-    numClientPorts:  Range.Inclusive = 1 to 1,
-    numManagerPorts: Range.Inclusive = 1 to 1) = new TLAdapterNode(clientFn, managerFn, numClientPorts, numManagerPorts)
-}
-
-class TLOutputNode extends BaseNode(TLImp)(
-    clientFn  = Some({case Seq(x) => x}),
-    managerFn = Some({case Seq(x) => x}),
-    numClientPorts  = 1 to 1,
-    numManagerPorts = 1 to 1)
 {
   override def connectOut = bundleOut
   override def connectIn  = bundleOut
 }
 
-object TLOutputNode
+class InputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
-{
+  extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
-  def apply() = new TLOutputNode()
-}
-
-class TLInputNode extends BaseNode(TLImp)(
-    clientFn  = Some({case Seq(x) => x}),
-    managerFn = Some({case Seq(x) => x}),
-    numClientPorts  = 1 to 1,
-    numManagerPorts = 1 to 1)
 {
   override def connectOut = bundleIn
   override def connectIn  = bundleIn
 }
 
-object TLInputNode
+class SourceNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
+  extends BaseNode(imp)(Some{case Seq() => po}, None, num, 0 to 0)
 {
-  def apply() = new TLInputNode()
+  require (num.end >= 1)
+}
+
+class SinkNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
+  extends BaseNode(imp)(None, Some{case Seq() => pi}, 0 to 0, num)
+{
+  require (num.end >= 1)
+}
+
+class InteriorNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])
+  (oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
+  extends BaseNode(imp)(Some(oFn), Some(iFn), numPO, numPI)
+{
+  require (numPO.end >= 1)
+  require (numPI.end >= 1)
 }

uncore/src/main/scala/tilelink2/Operations.scala

@@ -431,26 +431,3 @@ class TLEdgeIn(
     d
   }
 }
-
-object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
-{
-  def edgeO(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(po, pi)
-  def edgeI(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeIn  = new TLEdgeIn(po, pi)
-  def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
-    require (!eo.isEmpty)
-    Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
-  }
-  def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
-    require (!ei.isEmpty)
-    Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
-  }
-
-  def connect(bo: TLBundle, eo: TLEdgeOut, bi: TLBundle, ei: TLEdgeIn)(implicit sourceInfo: SourceInfo): Unit = {
-    TLMonitor.legalize(bo, eo, bi, ei, sourceInfo)
-    bi <> bo
-    val mask = ~UInt(ei.manager.beatBytes - 1)
-    bi.a.bits.address := (mask & bo.a.bits.address)
-    bo.b.bits.address := (mask & bi.b.bits.address)
-    bi.c.bits.address := (mask & bo.c.bits.address)
-  }
-}

uncore/src/main/scala/tilelink2/TLNodes.scala

@@ -0,0 +1,46 @@
+// See LICENSE for license details.
+
+package uncore.tilelink2
+
+import Chisel._
+import scala.collection.mutable.ListBuffer
+import chisel3.internal.sourceinfo.SourceInfo
+
+object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
+{
+  def edgeO(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(po, pi)
+  def edgeI(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeIn  = new TLEdgeIn(po, pi)
+  def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
+    require (!eo.isEmpty)
+    Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
+  }
+  def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
+    require (!ei.isEmpty)
+    Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
+  }
+
+  def connect(bo: TLBundle, eo: TLEdgeOut, bi: TLBundle, ei: TLEdgeIn)(implicit sourceInfo: SourceInfo): Unit = {
+    TLMonitor.legalize(bo, eo, bi, ei, sourceInfo)
+    bi <> bo
+    val mask = ~UInt(ei.manager.beatBytes - 1)
+    bi.a.bits.address := (mask & bo.a.bits.address)
+    bo.b.bits.address := (mask & bi.b.bits.address)
+    bi.c.bits.address := (mask & bo.c.bits.address)
+  }
+}
+
+case class TLOutputNode() extends OutputNode(TLImp)
+case class TLInputNode() extends InputNode(TLImp)
+
+case class TLClientNode(params: TLClientParameters, numPorts: Range.Inclusive = 1 to 1)
+  extends SourceNode(TLImp)(TLClientPortParameters(Seq(params)), numPorts)
+
+case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1)
+  extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes), numPorts)
+
+case class TLAdapterNode(
+  clientFn:        Seq[TLClientPortParameters]  => TLClientPortParameters,
+  managerFn:       Seq[TLManagerPortParameters] => TLManagerPortParameters,
+  numClientPorts:  Range.Inclusive = 1 to 1,
+  numManagerPorts: Range.Inclusive = 1 to 1)
+  extends InteriorNode(TLImp)(clientFn, managerFn, numClientPorts, numManagerPorts)