riscv/rocket-chip
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Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations)

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Stephen Twigg
2014-01-21 14:48:04 -08:00
parent 37b86c89fa
commit ee0c4ca291
8 changed files with 8 additions and 8 deletions
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2
chisel

Submodule chisel updated: 4483d41471...ae1d1de821

2
csrc/emulator.cc
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@@ -125,7 +125,7 @@ int main(int argc, char** argv)
} }
if (log) if (log)
tile.print(stderr); tile.print(stderr, stderr);
if (vcd) if (vcd)
tile.dump(vcdfile, trace_count); tile.dump(vcdfile, trace_count);

2
riscv-tests

Submodule riscv-tests updated: fdf5e6f97d...7356626efe

2
riscv-tools

Submodule riscv-tools updated: 20b2d997f0...323639fa2a

2
rocket

Submodule rocket updated: 5555e6f748...9aa03938c0

2
src/main/scala/RocketChip.scala
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@@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
val mem_backup = new ioMemSerialized(htif_width) val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT) val mem_backup_en = Bool(INPUT)
} }
val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif

2
src/main/scala/fpga.scala
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@@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
} }
val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif outmemsys.io.incoherent := incoherentWithHtif

2
uncore

Submodule uncore updated: ac4a5373c6...a58265755f