From ee0c4ca291076baef7944071d76fe82d42de7e43 Mon Sep 17 00:00:00 2001 From: Stephen Twigg Date: Tue, 21 Jan 2014 14:48:04 -0800 Subject: [PATCH] Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations) --- chisel | 2 +- csrc/emulator.cc | 2 +- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 2 +- uncore | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/chisel b/chisel index 4483d414..ae1d1de8 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 4483d41471e4cb8e77b61f3f13255f4d59425d61 +Subproject commit ae1d1de82188f0a1d79a4e8eb613743942a13eb3 diff --git a/csrc/emulator.cc b/csrc/emulator.cc index 3765e161..587036b9 100644 --- a/csrc/emulator.cc +++ b/csrc/emulator.cc @@ -125,7 +125,7 @@ int main(int argc, char** argv) } if (log) - tile.print(stderr); + tile.print(stderr, stderr); if (vcd) tile.dump(vcdfile, trace_count); diff --git a/riscv-tests b/riscv-tests index fdf5e6f9..7356626e 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit fdf5e6f97d53722d7ec44c4591f1ab740a092808 +Subproject commit 7356626efe5c331f77202e6e1d875c85c4b4588a diff --git a/riscv-tools b/riscv-tools index 20b2d997..323639fa 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 20b2d997f01a3c879b0158ab1af3f4947628bb36 +Subproject commit 323639fa2ae51fbc60c655d2a16611672809beef diff --git a/rocket b/rocket index 5555e6f7..9aa03938 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 5555e6f7485387ed8fba69c6ae3935fabdf8c6e3 +Subproject commit 9aa03938c05323e292c79b8b5fb4a49e911183d7 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 7733067c..083220d8 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf val mem_backup = new ioMemSerialized(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 3aab9d29..e491caba 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/uncore b/uncore index ac4a5373..a5826575 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit ac4a5373c69c04a003bebe54fb7eca7387a43e4d +Subproject commit a58265755fcb90aebe5377cb9b7343732fd14b9a