From eadf4e9fcc968ce3af5024e5455eb21a1cd15228 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Sat, 29 Jul 2017 00:03:24 -0700
Subject: [PATCH] Revert "tile: add option for tile boundary buffers"

This reverts commit b64b87ad0778582bb8583567d1d653f61f230a28.

The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
---
 src/main/scala/tile/RocketTile.scala | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index 7afcb64d..4bb6661e 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -17,8 +17,7 @@ case class RocketTileParams(
     dcache: Option[DCacheParams] = Some(DCacheParams()),
     rocc: Seq[RoCCParams] = Nil,
     btb: Option[BTBParams] = Some(BTBParams()),
-    dataScratchpadBytes: Int = 0,
-    boundaryBufferParams: BufferParams = BufferParams.flow) extends TileParams {
+    dataScratchpadBytes: Int = 0) extends TileParams {
   require(icache.isDefined)
   require(dcache.isDefined)
 }
@@ -172,11 +171,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
   val periphIntNode  = IntInputNode()
   val coreIntNode    = IntInputNode()
   val intXbar = LazyModule(new IntXbar)
-  val masterBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
-  val slaveBuffer = LazyModule(new TLBuffer(rtp.boundaryBufferParams))
 
-  masterBuffer.node :=* rocket.masterNode
-  rocket.slaveNode connectButDontMonitorSlaves slaveBuffer.node
   rocket.intNode := intXbar.intnode
 
   lazy val module = new LazyModuleImp(this) {
@@ -195,10 +190,10 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
 
 class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLOutputNode()
-  masterNode :=* masterBuffer.node
+  masterNode :=* rocket.masterNode
 
   val slaveNode = new TLInputNode() { override def reverse = true }
-  slaveBuffer.node connectButDontMonitorSlaves slaveNode
+  rocket.slaveNode connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers.
   // Others need no synchronization.
@@ -213,12 +208,12 @@ class SyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters)
 class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLAsyncOutputNode()
   val source = LazyModule(new TLAsyncCrossingSource)
-  source.node :=* masterBuffer.node
+  source.node :=* rocket.masterNode
   masterNode :=* source.node
 
   val slaveNode = new TLAsyncInputNode() { override def reverse = true }
   val sink = LazyModule(new TLAsyncCrossingSink)
-  slaveBuffer.node connectButDontMonitorSlaves sink.node
+  rocket.slaveNode connectButDontMonitorSlaves sink.node
   sink.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers,
@@ -237,12 +232,12 @@ class AsyncRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters
 class RationalRocketTile(rtp: RocketTileParams, hartid: Int)(implicit p: Parameters) extends RocketTileWrapper(rtp, hartid) {
   val masterNode = TLRationalOutputNode()
   val source = LazyModule(new TLRationalCrossingSource)
-  source.node :=* masterBuffer.node
+  source.node :=* rocket.masterNode
   masterNode :=* source.node
 
   val slaveNode = new TLRationalInputNode() { override def reverse = true }
   val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
-  slaveBuffer.node connectButDontMonitorSlaves sink.node
+  rocket.slaveNode connectButDontMonitorSlaves sink.node
   sink.node connectButDontMonitorSlaves slaveNode
 
   // Fully async interrupts need synchronizers.