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subsystem: more buswrapper methods

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This commit is contained in:
Henry Cook 2018-02-21 14:40:26 -08:00
parent e237f72539
commit eaa908d44f
3 changed files with 32 additions and 5 deletions
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9
src/main/scala/subsystem/MemoryBus.scala
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@ -56,7 +56,14 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
} }
} }
def toDRAMController[D,U,E,B <: Data]( def toDRAMController(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLInwardNode) {
to("memory_controller" named name) { gen := bufferTo(buffer) }
}
def toDRAMControllerPort[D,U,E,B <: Data](
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.none) buffer: BufferParams = BufferParams.none)
(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = { (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {

2
src/main/scala/subsystem/Ports.scala
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@ -52,7 +52,7 @@ trait HasMasterAXI4MemPort { this: BaseSubsystem =>
}) })
memBuses.map { m => memBuses.map { m =>
mem_axi4 := m.toDRAMController(Some(portName)) { mem_axi4 := m.toDRAMControllerPort(Some(portName)) {
(AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4()) (AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
} }
} }

26
src/main/scala/subsystem/SystemBus.scala
View File

@ -23,6 +23,9 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
private def bufferTo(buffer: BufferParams): TLOutwardNode = private def bufferTo(buffer: BufferParams): TLOutwardNode =
TLBuffer(buffer) :*= delayNode :*= outwardNode TLBuffer(buffer) :*= delayNode :*= outwardNode
private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
def toPeripheryBus(buffer: BufferParams = BufferParams.none) def toPeripheryBus(buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = { (gen: => TLNode): TLOutwardNode = {
to("pbus") { to("pbus") {
@ -47,6 +50,13 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
to("slave" named name) { gen :*= master_splitter.node } to("slave" named name) { gen :*= master_splitter.node }
} }
def toFixedWidthSlave(
name: Option[String] = None,
buffer: BufferParams = BufferParams.none)
(gen: => TLNode): TLOutwardNode = {
to("slave" named name) { gen :*= fixedWidthTo(buffer) }
}
def toVariableWidthSlave( def toVariableWidthSlave(
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.default) buffer: BufferParams = BufferParams.default)
@ -79,9 +89,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
name: Option[String] = None, name: Option[String] = None,
buffer: BufferParams = BufferParams.default) buffer: BufferParams = BufferParams.default)
(gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = { (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
to("port" named name) { to("port" named name) { gen := fixedWidthTo(buffer) }
gen := TLWidthWidget(params.beatBytes) := bufferTo(buffer)
}
} }
def fromPort[D,U,E,B <: Data]( def fromPort[D,U,E,B <: Data](
@ -95,4 +103,16 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
} }
} }
def fromMaster(
name: Option[String] = None,
buffers: Int = 0)
(gen: => TLNode): TLInwardNode = {
from("master" named name) {
(List(
master_splitter.node,
TLFIFOFixer(TLFIFOFixer.all)) ++
TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
}
}
} }