diff --git a/src/main/scala/subsystem/MemoryBus.scala b/src/main/scala/subsystem/MemoryBus.scala
index 8d34fddd..d86864bf 100644
--- a/src/main/scala/subsystem/MemoryBus.scala
+++ b/src/main/scala/subsystem/MemoryBus.scala
@@ -56,7 +56,14 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
     }
   }
 
-  def toDRAMController[D,U,E,B <: Data](
+  def toDRAMController(
+        name: Option[String] = None,
+        buffer: BufferParams = BufferParams.none)
+      (gen: => TLInwardNode) {
+    to("memory_controller" named name) { gen := bufferTo(buffer) }
+  }
+
+  def toDRAMControllerPort[D,U,E,B <: Data](
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.none)
       (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
diff --git a/src/main/scala/subsystem/Ports.scala b/src/main/scala/subsystem/Ports.scala
index 40d38a34..c29f5d74 100644
--- a/src/main/scala/subsystem/Ports.scala
+++ b/src/main/scala/subsystem/Ports.scala
@@ -52,7 +52,7 @@ trait HasMasterAXI4MemPort { this: BaseSubsystem =>
   })
 
   memBuses.map { m =>
-    mem_axi4 := m.toDRAMController(Some(portName)) {
+    mem_axi4 := m.toDRAMControllerPort(Some(portName)) {
       (AXI4UserYanker() := AXI4IdIndexer(params.idBits) := TLToAXI4())
     }
   }
diff --git a/src/main/scala/subsystem/SystemBus.scala b/src/main/scala/subsystem/SystemBus.scala
index 819a3be9..cc69ebde 100644
--- a/src/main/scala/subsystem/SystemBus.scala
+++ b/src/main/scala/subsystem/SystemBus.scala
@@ -23,6 +23,9 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
   private def bufferTo(buffer: BufferParams): TLOutwardNode =
     TLBuffer(buffer) :*= delayNode :*= outwardNode
 
+  private def fixedWidthTo(buffer: BufferParams): TLOutwardNode =
+    TLWidthWidget(params.beatBytes) :*= bufferTo(buffer)
+
   def toPeripheryBus(buffer: BufferParams = BufferParams.none)
                     (gen: => TLNode): TLOutwardNode = {
     to("pbus") {
@@ -47,6 +50,13 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     to("slave" named name) { gen :*= master_splitter.node }
   }
 
+  def toFixedWidthSlave(
+        name: Option[String] = None,
+        buffer: BufferParams = BufferParams.none)
+      (gen: => TLNode): TLOutwardNode = {
+    to("slave" named name) { gen :*= fixedWidthTo(buffer) }
+  }
+
   def toVariableWidthSlave(
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.default)
@@ -79,9 +89,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
         name: Option[String] = None,
         buffer: BufferParams = BufferParams.default)
       (gen: => NodeHandle[TLClientPortParameters,TLManagerPortParameters,TLEdgeIn,TLBundle,D,U,E,B]): OutwardNodeHandle[D,U,E,B] = {
-    to("port" named name) {
-      gen := TLWidthWidget(params.beatBytes) := bufferTo(buffer)
-    }
+    to("port" named name) { gen := fixedWidthTo(buffer) }
   }
 
   def fromPort[D,U,E,B <: Data](
@@ -95,4 +103,16 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
         TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
     }
   }
+
+  def fromMaster(
+        name: Option[String] = None,
+        buffers: Int = 0)
+      (gen: => TLNode): TLInwardNode = {
+    from("master" named name) {
+      (List(
+        master_splitter.node,
+        TLFIFOFixer(TLFIFOFixer.all)) ++
+        TLBuffer.chain(buffers)).reduce(_ :=* _) :=* gen
+    }
+  }
 }