riscv/rocket-chip
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TileLink utility objects should not take implicit parameters

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We have a handful of TileLink-related helper objects
(wrappers, unwrappers, width adapters, and enqueuers). Previously, using
them could be error-prone, because you had to make sure the implicit
parameters they took in had the same TLId as the TileLinkIO bundles
passed in as inputs. This is rather silly, we should just use the
parameters in the bundle.
This commit is contained in:
Howard Mao
2016-09-23 10:06:09 -07:00
parent 803739a95c
commit ea9f0a868f
6 changed files with 45 additions and 43 deletions
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26
src/main/scala/rocketchip/Periphery.scala
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@ -52,8 +52,8 @@ case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4)
case object PeripheryBusKey extends Field[PeripheryBusConfig]
object PeripheryUtils {
def addQueueAXI(source: NastiIO)(implicit p: Parameters) = {
val sink = Wire(new NastiIO)
def addQueueAXI(source: NastiIO) = {
val sink = Wire(source)
sink.ar <> Queue(source.ar, 1)
sink.aw <> Queue(source.aw, 1)
sink.w <> Queue(source.w)
@ -61,13 +61,13 @@ object PeripheryUtils {
source.b <> Queue(sink.b, 1)
sink
}
def convertTLtoAXI(tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
val bridge = Module(new NastiIOTileLinkIOConverter())
def convertTLtoAXI(tl: ClientUncachedTileLinkIO) = {
val bridge = Module(new NastiIOTileLinkIOConverter()(tl.p))
bridge.io.tl <> tl
addQueueAXI(bridge.io.nasti)
}
def convertTLtoAHB(tl: ClientUncachedTileLinkIO, atomics: Boolean)(implicit p: Parameters) = {
val bridge = Module(new AHBBridge(atomics))
def convertTLtoAHB(tl: ClientUncachedTileLinkIO, atomics: Boolean) = {
val bridge = Module(new AHBBridge(atomics)(tl.p))
bridge.io.tl <> tl
bridge.io.ahb
}
@ -173,7 +173,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
// Abuse the fact that zip takes the shorter of the two lists
((io.mem_axi zip coreplexIO.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams)
val axi_sync = PeripheryUtils.convertTLtoAXI(mem)
axi_sync.ar.bits.cache := CACHE_NORMAL_NOCACHE_BUF
axi_sync.aw.bits.cache := CACHE_NORMAL_NOCACHE_BUF
axi <> (
@ -183,11 +183,11 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
}
(io.mem_ahb zip coreplexIO.master.mem) foreach { case (ahb, mem) =>
ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false)(outermostParams)
ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false)
}
(io.mem_tl zip coreplexIO.master.mem) foreach { case (tl, mem) =>
tl <> TileLinkEnqueuer(mem, 2)(outermostParams)
tl <> TileLinkEnqueuer(mem, 2)
}
}
@ -213,7 +213,7 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
val pBus: TileLinkRecursiveInterconnect
val mmio_ports = p(ExtMMIOPorts) map { port =>
TileLinkWidthAdapter(pBus.port(port.name), "MMIO_Outermost")
TileLinkWidthAdapter(pBus.port(port.name), innerMMIOParams)
}
val mmio_axi_start = 0
@ -227,17 +227,17 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
for (i <- 0 until mmio_ports.size) {
if (mmio_axi_start <= i && i < mmio_axi_end) {
val idx = i-mmio_axi_start
val axi_sync = PeripheryUtils.convertTLtoAXI(mmio_ports(i))(outermostMMIOParams)
val axi_sync = PeripheryUtils.convertTLtoAXI(mmio_ports(i))
io.mmio_axi(idx) <> (
if (!p(AsyncMMIOChannels)) axi_sync
else AsyncNastiTo(io.mmio_clk.get(idx), io.mmio_rst.get(idx), axi_sync)
)
} else if (mmio_ahb_start <= i && i < mmio_ahb_end) {
val idx = i-mmio_ahb_start
io.mmio_ahb(idx) <> PeripheryUtils.convertTLtoAHB(mmio_ports(i), atomics = true)(outermostMMIOParams)
io.mmio_ahb(idx) <> PeripheryUtils.convertTLtoAHB(mmio_ports(i), atomics = true)
} else if (mmio_tl_start <= i && i < mmio_tl_end) {
val idx = i-mmio_tl_start
io.mmio_tl(idx) <> TileLinkEnqueuer(mmio_ports(i), 2)(outermostMMIOParams)
io.mmio_tl(idx) <> TileLinkEnqueuer(mmio_ports(i), 2)
} else {
require(false, "Unconnected external MMIO port")
}