From ea9f0a868f204b88345afda5d1d0948b70b5978a Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 23 Sep 2016 10:06:09 -0700 Subject: [PATCH] TileLink utility objects should not take implicit parameters We have a handful of TileLink-related helper objects (wrappers, unwrappers, width adapters, and enqueuers). Previously, using them could be error-prone, because you had to make sure the implicit parameters they took in had the same TLId as the TileLinkIO bundles passed in as inputs. This is rather silly, we should just use the parameters in the bundle. --- src/main/scala/coreplex/BaseCoreplex.scala | 6 ++-- src/main/scala/coreplex/Coreplex.scala | 6 ++-- src/main/scala/rocketchip/Periphery.scala | 26 ++++++++-------- src/main/scala/uncore/agents/Agents.scala | 2 +- .../scala/uncore/converters/Tilelink.scala | 30 ++++++++++--------- src/main/scala/uncore/util/Enqueuer.scala | 18 +++++------ 6 files changed, 45 insertions(+), 43 deletions(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 86e3da4a..62ddc828 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -115,9 +115,9 @@ abstract class BaseCoreplexModule[+L <: BaseCoreplex, +B <: BaseCoreplexBundle]( val outerTLParams = p.alterPartial({ case TLId => "L2toMC" }) val backendBuffering = TileLinkDepths(0,0,0,0,0) for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) { - val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams)) - unwrap.io.in <> TileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams) - TileLinkWidthAdapter(icPort, unwrap.io.out) + val enqueued = TileLinkEnqueuer(bank.outerTL, backendBuffering) + val unwrapped = TileLinkIOUnwrapper(enqueued) + TileLinkWidthAdapter(icPort, unwrapped) } io.master.mem <> mem_ic.io.out diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index 7fbec799..2231ca00 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -15,9 +15,9 @@ trait DirectConnection { val ultBuffering = UncachedTileLinkDepths(1,2) (tiles zip uncoreTileIOs) foreach { case (tile, uncore) => - (uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering)(t.p) } - (uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering)(t.p) } - tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1)(uncore.slave.get.p) } + (uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) } + (uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) } + tile.io.slave.foreach { _ <> TileLinkEnqueuer(uncore.slave.get, 1) } tile.io.interrupts <> uncore.interrupts diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index d4667f54..8ff4e15a 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -52,8 +52,8 @@ case class PeripheryBusConfig(arithAMO: Boolean, beatBytes: Int = 4) case object PeripheryBusKey extends Field[PeripheryBusConfig] object PeripheryUtils { - def addQueueAXI(source: NastiIO)(implicit p: Parameters) = { - val sink = Wire(new NastiIO) + def addQueueAXI(source: NastiIO) = { + val sink = Wire(source) sink.ar <> Queue(source.ar, 1) sink.aw <> Queue(source.aw, 1) sink.w <> Queue(source.w) @@ -61,13 +61,13 @@ object PeripheryUtils { source.b <> Queue(sink.b, 1) sink } - def convertTLtoAXI(tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = { - val bridge = Module(new NastiIOTileLinkIOConverter()) + def convertTLtoAXI(tl: ClientUncachedTileLinkIO) = { + val bridge = Module(new NastiIOTileLinkIOConverter()(tl.p)) bridge.io.tl <> tl addQueueAXI(bridge.io.nasti) } - def convertTLtoAHB(tl: ClientUncachedTileLinkIO, atomics: Boolean)(implicit p: Parameters) = { - val bridge = Module(new AHBBridge(atomics)) + def convertTLtoAHB(tl: ClientUncachedTileLinkIO, atomics: Boolean) = { + val bridge = Module(new AHBBridge(atomics)(tl.p)) bridge.io.tl <> tl bridge.io.ahb } @@ -173,7 +173,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters { // Abuse the fact that zip takes the shorter of the two lists ((io.mem_axi zip coreplexIO.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) => - val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams) + val axi_sync = PeripheryUtils.convertTLtoAXI(mem) axi_sync.ar.bits.cache := CACHE_NORMAL_NOCACHE_BUF axi_sync.aw.bits.cache := CACHE_NORMAL_NOCACHE_BUF axi <> ( @@ -183,11 +183,11 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters { } (io.mem_ahb zip coreplexIO.master.mem) foreach { case (ahb, mem) => - ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false)(outermostParams) + ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false) } (io.mem_tl zip coreplexIO.master.mem) foreach { case (tl, mem) => - tl <> TileLinkEnqueuer(mem, 2)(outermostParams) + tl <> TileLinkEnqueuer(mem, 2) } } @@ -213,7 +213,7 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters { val pBus: TileLinkRecursiveInterconnect val mmio_ports = p(ExtMMIOPorts) map { port => - TileLinkWidthAdapter(pBus.port(port.name), "MMIO_Outermost") + TileLinkWidthAdapter(pBus.port(port.name), innerMMIOParams) } val mmio_axi_start = 0 @@ -227,17 +227,17 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters { for (i <- 0 until mmio_ports.size) { if (mmio_axi_start <= i && i < mmio_axi_end) { val idx = i-mmio_axi_start - val axi_sync = PeripheryUtils.convertTLtoAXI(mmio_ports(i))(outermostMMIOParams) + val axi_sync = PeripheryUtils.convertTLtoAXI(mmio_ports(i)) io.mmio_axi(idx) <> ( if (!p(AsyncMMIOChannels)) axi_sync else AsyncNastiTo(io.mmio_clk.get(idx), io.mmio_rst.get(idx), axi_sync) ) } else if (mmio_ahb_start <= i && i < mmio_ahb_end) { val idx = i-mmio_ahb_start - io.mmio_ahb(idx) <> PeripheryUtils.convertTLtoAHB(mmio_ports(i), atomics = true)(outermostMMIOParams) + io.mmio_ahb(idx) <> PeripheryUtils.convertTLtoAHB(mmio_ports(i), atomics = true) } else if (mmio_tl_start <= i && i < mmio_tl_end) { val idx = i-mmio_tl_start - io.mmio_tl(idx) <> TileLinkEnqueuer(mmio_ports(i), 2)(outermostMMIOParams) + io.mmio_tl(idx) <> TileLinkEnqueuer(mmio_ports(i), 2) } else { require(false, "Unconnected external MMIO port") } diff --git a/src/main/scala/uncore/agents/Agents.scala b/src/main/scala/uncore/agents/Agents.scala index fe10ca23..2dc78d82 100644 --- a/src/main/scala/uncore/agents/Agents.scala +++ b/src/main/scala/uncore/agents/Agents.scala @@ -139,7 +139,7 @@ abstract class ManagerCoherenceAgent(implicit p: Parameters) extends CoherenceAg with HasCoherenceAgentWiringHelpers { val io = new ManagerTLIO def innerTL = io.inner - def outerTL = TileLinkIOWrapper(io.outer)(p.alterPartial({case TLId => p(OuterTLId)})) + def outerTL = TileLinkIOWrapper(io.outer) def incoherent = io.incoherent } diff --git a/src/main/scala/uncore/converters/Tilelink.scala b/src/main/scala/uncore/converters/Tilelink.scala index f14498b7..a9a7eb71 100644 --- a/src/main/scala/uncore/converters/Tilelink.scala +++ b/src/main/scala/uncore/converters/Tilelink.scala @@ -10,13 +10,13 @@ import cde.Parameters /** Utilities for safely wrapping a *UncachedTileLink by pinning probe.ready and release.valid low */ object TileLinkIOWrapper { - def apply(tl: ClientUncachedTileLinkIO)(implicit p: Parameters): ClientTileLinkIO = { - val conv = Module(new ClientTileLinkIOWrapper) + def apply(tl: ClientUncachedTileLinkIO): ClientTileLinkIO = { + val conv = Module(new ClientTileLinkIOWrapper()(tl.p)) conv.io.in <> tl conv.io.out } - def apply(tl: UncachedTileLinkIO)(implicit p: Parameters): TileLinkIO = { - val conv = Module(new TileLinkIOWrapper) + def apply(tl: UncachedTileLinkIO): TileLinkIO = { + val conv = Module(new TileLinkIOWrapper()(tl.p)) conv.io.in <> tl conv.io.out } @@ -150,29 +150,31 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) { } object TileLinkIOUnwrapper { - def apply(in: ClientTileLinkIO)(implicit p: Parameters): ClientUncachedTileLinkIO = { - val unwrapper = Module(new ClientTileLinkIOUnwrapper) + def apply(in: ClientTileLinkIO): ClientUncachedTileLinkIO = { + val unwrapper = Module(new ClientTileLinkIOUnwrapper()(in.p)) unwrapper.io.in <> in unwrapper.io.out } } object TileLinkWidthAdapter { - def apply(in: ClientUncachedTileLinkIO, outerId: String)(implicit p: Parameters) = { - val outerDataBits = p(TLKey(outerId)).dataBitsPerBeat + def apply(in: ClientUncachedTileLinkIO, outerParams: Parameters) = { + val outerTLId = outerParams(TLId) + val outerDataBits = outerParams(TLKey(outerTLId)).dataBitsPerBeat + implicit val p = outerParams if (outerDataBits > in.tlDataBits) { - val widener = Module(new TileLinkIOWidener(in.p(TLId), outerId)) + val widener = Module(new TileLinkIOWidener(in.p(TLId), outerTLId)) widener.io.in <> in widener.io.out } else if (outerDataBits < in.tlDataBits) { - val narrower = Module(new TileLinkIONarrower(in.p(TLId), outerId)) + val narrower = Module(new TileLinkIONarrower(in.p(TLId), outerTLId)) narrower.io.in <> in narrower.io.out } else { in } } - def apply(out: ClientUncachedTileLinkIO, in: ClientUncachedTileLinkIO)(implicit p: Parameters): Unit = { + def apply(out: ClientUncachedTileLinkIO, in: ClientUncachedTileLinkIO): Unit = { require(out.tlDataBits * out.tlDataBeats == in.tlDataBits * in.tlDataBeats) - out <> apply(in, out.p(TLId)) + out <> apply(in, out.p) } } @@ -684,8 +686,8 @@ class TileLinkFragmenter(depth: Int = 1)(implicit p: Parameters) extends TLModul object TileLinkFragmenter { // Pass the source/client to fragment - def apply(source: ClientUncachedTileLinkIO, depth: Int = 1)(implicit p: Parameters): ClientUncachedTileLinkIO = { - val fragmenter = Module(new TileLinkFragmenter(depth)) + def apply(source: ClientUncachedTileLinkIO, depth: Int = 1): ClientUncachedTileLinkIO = { + val fragmenter = Module(new TileLinkFragmenter(depth)(source.p)) fragmenter.io.in <> source fragmenter.io.out } diff --git a/src/main/scala/uncore/util/Enqueuer.scala b/src/main/scala/uncore/util/Enqueuer.scala index 71c1d8c1..3018821d 100644 --- a/src/main/scala/uncore/util/Enqueuer.scala +++ b/src/main/scala/uncore/util/Enqueuer.scala @@ -22,29 +22,29 @@ class TileLinkEnqueuer(depths: TileLinkDepths)(implicit p: Parameters) extends M } object TileLinkEnqueuer { - def apply(in: TileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): TileLinkIO = { - val t = Module(new TileLinkEnqueuer(depths)) + def apply(in: TileLinkIO, depths: TileLinkDepths): TileLinkIO = { + val t = Module(new TileLinkEnqueuer(depths)(in.p)) t.io.client <> in t.io.manager } - def apply(in: TileLinkIO, depth: Int)(implicit p: Parameters): TileLinkIO = { + def apply(in: TileLinkIO, depth: Int): TileLinkIO = { apply(in, TileLinkDepths(depth, depth, depth, depth, depth)) } - def apply(in: ClientTileLinkIO, depths: TileLinkDepths)(implicit p: Parameters): ClientTileLinkIO = { - val t = Module(new ClientTileLinkEnqueuer(depths)) + def apply(in: ClientTileLinkIO, depths: TileLinkDepths): ClientTileLinkIO = { + val t = Module(new ClientTileLinkEnqueuer(depths)(in.p)) t.io.inner <> in t.io.outer } - def apply(in: ClientTileLinkIO, depth: Int)(implicit p: Parameters): ClientTileLinkIO = { + def apply(in: ClientTileLinkIO, depth: Int): ClientTileLinkIO = { apply(in, TileLinkDepths(depth, depth, depth, depth, depth)) } - def apply(in: ClientUncachedTileLinkIO, depths: UncachedTileLinkDepths)(implicit p: Parameters): ClientUncachedTileLinkIO = { - val t = Module(new ClientUncachedTileLinkEnqueuer(depths)) + def apply(in: ClientUncachedTileLinkIO, depths: UncachedTileLinkDepths): ClientUncachedTileLinkIO = { + val t = Module(new ClientUncachedTileLinkEnqueuer(depths)(in.p)) t.io.inner <> in t.io.outer } - def apply(in: ClientUncachedTileLinkIO, depth: Int)(implicit p: Parameters): ClientUncachedTileLinkIO = { + def apply(in: ClientUncachedTileLinkIO, depth: Int): ClientUncachedTileLinkIO = { apply(in, UncachedTileLinkDepths(depth, depth)) } }