riscv/rocket-chip
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Use vlsi_mem_gen for verilator flow

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This commit is contained in:
Andrew Waterman 2017-08-07 20:36:22 -07:00
parent b0f32c8f09
commit ea4b1bc349
3 changed files with 15 additions and 6 deletions
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2
Makefrag
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@ -10,6 +10,8 @@ CONFIG ?= DefaultConfig
# TODO: For now must match rocketchip.Generator # TODO: For now must match rocketchip.Generator
long_name = $(PROJECT).$(CONFIG) long_name = $(PROJECT).$(CONFIG)
VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
CXX ?= g++ CXX ?= g++
CXXFLAGS := -O1 CXXFLAGS := -O1
JVM_MEMORY ?= 2G JVM_MEMORY ?= 2G

18
emulator/Makefrag-verilator
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@ -2,7 +2,9 @@
# Verilator Generation # Verilator Generation
#-------------------------------------------------------------------- #--------------------------------------------------------------------
firrtl = $(generated_dir)/$(long_name).fir firrtl = $(generated_dir)/$(long_name).fir
verilog = $(generated_dir)/$(long_name).v verilog = \
$(generated_dir)/$(long_name).v \
$(generated_dir)/$(long_name).behav_srams.v \
.SECONDARY: $(firrtl) $(verilog) .SECONDARY: $(firrtl) $(verilog)
@ -10,9 +12,14 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
%.v: %.fir $(FIRRTL_JAR) %.v %.conf: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@) mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
cd $(generated_dir) && \
$(VLSI_MEM_GEN) $(generated_dir)/$(long_name).conf > $@.tmp && \
mv -f $@.tmp $@
# Build and install our own Verilator, to work around versionining issues. # Build and install our own Verilator, to work around versionining issues.
VERILATOR_VERSION=3.904 VERILATOR_VERSION=3.904
@ -47,6 +54,7 @@ verilator: $(INSTALLED_VERILATOR)
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
VERILATOR_FLAGS := --top-module $(MODEL) \ VERILATOR_FLAGS := --top-module $(MODEL) \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
--output-split 20000 \ --output-split 20000 \
--output-split-cfuncs 20000 \ --output-split-cfuncs 20000 \
@ -62,13 +70,13 @@ model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
$(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR) $(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir)/$(long_name) mkdir -p $(generated_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \ -o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir) -include $(model_header)" -CFLAGS "-I$(generated_dir) -include $(model_header)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk $(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
$(emu_debug): $(verilog) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR) $(emu_debug): $(verilog) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(long_name) mkdir -p $(generated_dir_debug)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \ -o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)" -CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk $(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk

1
vsim/Makefile
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@ -11,7 +11,6 @@ default: all
base_dir = $(abspath ..) base_dir = $(abspath ..)
generated_dir = $(abspath ./generated-src) generated_dir = $(abspath ./generated-src)
VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
mem_gen = $(VLSI_MEM_GEN) mem_gen = $(VLSI_MEM_GEN)
sim_dir = . sim_dir = .
output_dir = $(sim_dir)/output output_dir = $(sim_dir)/output