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Merge pull request #1135 from freechipsproject/decoupled-loop-fix

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TileLink compliance: d_bits may not depend on d_ready
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Wesley W. Terpstra 2017-11-30 18:21:37 -08:00 committed by GitHub
commit ea03f71f97
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2 changed files with 14 additions and 12 deletions
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14
src/main/scala/devices/debug/Debug.scala
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@ -249,11 +249,11 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par
*/ */
// Local reg mapper function : Notify when written, but give the value as well. // Local reg mapper function : Notify when written, but give the value as well.
object WNotify { object WNotifyWire {
def apply(n: Int, value: UInt, set: Bool) : RegField = { def apply(n: Int, value: UInt, set: Bool) : RegField = {
RegField(n, value, RegWriteFn((valid, data) => { RegField(n, UInt(0), RegWriteFn((valid, data) => {
set := valid set := valid
when(valid) {value := data} value := data
Bool(true) Bool(true)
})) }))
} }
@ -881,10 +881,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
tlNode.regmap( tlNode.regmap(
// This memory is writable. // This memory is writable.
HALTED -> Seq(WNotify(sbIdWidth, hartHaltedId, hartHaltedWrEn)), HALTED -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn)),
GOING -> Seq(WNotify(sbIdWidth, hartGoingId, hartGoingWrEn)), GOING -> Seq(WNotifyWire(sbIdWidth, hartGoingId, hartGoingWrEn)),
RESUMING -> Seq(WNotify(sbIdWidth, hartResumingId, hartResumingWrEn)), RESUMING -> Seq(WNotifyWire(sbIdWidth, hartResumingId, hartResumingWrEn)),
EXCEPTION -> Seq(WNotify(sbIdWidth, hartExceptionId, hartExceptionWrEn)), EXCEPTION -> Seq(WNotifyWire(sbIdWidth, hartExceptionId, hartExceptionWrEn)),
DATA -> abstractDataMem.map(x => RegField(8, x)), DATA -> abstractDataMem.map(x => RegField(8, x)),
PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)), PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)),

10
src/main/scala/regmapper/RegField.scala
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@ -113,13 +113,15 @@ object RegField
// than the intended bus width of the device (atomic updates are impossible). // than the intended bus width of the device (atomic updates are impossible).
def bytes(reg: UInt, numBytes: Int): Seq[RegField] = { def bytes(reg: UInt, numBytes: Int): Seq[RegField] = {
val pad = reg | UInt(0, width = 8*numBytes) val pad = reg | UInt(0, width = 8*numBytes)
val bytes = Wire(init = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }) val oldBytes = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }
val newBytes = Wire(init = oldBytes)
val valids = Wire(init = Vec.fill(numBytes) { Bool(false) }) val valids = Wire(init = Vec.fill(numBytes) { Bool(false) })
when (valids.reduce(_ || _)) { reg := bytes.asUInt } when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
bytes.zipWithIndex.map { case (b, i) => RegField(8, b, Seq.tabulate(numBytes) { i =>
RegField(8, oldBytes(i),
RegWriteFn((valid, data) => { RegWriteFn((valid, data) => {
valids(i) := valid valids(i) := valid
when (valid) { bytes(i) := data } when (valid) { newBytes(i) := data }
Bool(true) Bool(true)
}))}} }))}}