diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
index 12dc7a4d..a0da5a04 100644
--- a/src/main/scala/devices/debug/Debug.scala
+++ b/src/main/scala/devices/debug/Debug.scala
@@ -249,11 +249,11 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par
   */
 
 // Local reg mapper function : Notify when written, but give the value as well.  
-object WNotify {
+object WNotifyWire {
   def apply(n: Int, value: UInt, set: Bool) : RegField = {
-    RegField(n, value, RegWriteFn((valid, data) => {
+    RegField(n, UInt(0), RegWriteFn((valid, data) => {
       set := valid
-      when(valid) {value := data}
+      value := data
       Bool(true)
     }))
   }
@@ -881,10 +881,10 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
 
     tlNode.regmap(
       // This memory is writable.
-      HALTED      -> Seq(WNotify(sbIdWidth, hartHaltedId, hartHaltedWrEn)),
-      GOING       -> Seq(WNotify(sbIdWidth, hartGoingId,  hartGoingWrEn)),
-      RESUMING    -> Seq(WNotify(sbIdWidth, hartResumingId,  hartResumingWrEn)),
-      EXCEPTION   -> Seq(WNotify(sbIdWidth, hartExceptionId,  hartExceptionWrEn)),
+      HALTED      -> Seq(WNotifyWire(sbIdWidth, hartHaltedId, hartHaltedWrEn)),
+      GOING       -> Seq(WNotifyWire(sbIdWidth, hartGoingId,  hartGoingWrEn)),
+      RESUMING    -> Seq(WNotifyWire(sbIdWidth, hartResumingId,  hartResumingWrEn)),
+      EXCEPTION   -> Seq(WNotifyWire(sbIdWidth, hartExceptionId,  hartExceptionWrEn)),
       DATA        -> abstractDataMem.map(x => RegField(8, x)),
       PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)),
 
diff --git a/src/main/scala/regmapper/RegField.scala b/src/main/scala/regmapper/RegField.scala
index 3cf0caa8..16212c24 100644
--- a/src/main/scala/regmapper/RegField.scala
+++ b/src/main/scala/regmapper/RegField.scala
@@ -113,13 +113,15 @@ object RegField
   // than the intended bus width of the device (atomic updates are impossible).
   def bytes(reg: UInt, numBytes: Int): Seq[RegField] = {
     val pad = reg | UInt(0, width = 8*numBytes)
-    val bytes = Wire(init = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) })
+    val oldBytes = Vec.tabulate(numBytes) { i => pad(8*(i+1)-1, 8*i) }
+    val newBytes = Wire(init = oldBytes)
     val valids = Wire(init = Vec.fill(numBytes) { Bool(false) })
-    when (valids.reduce(_ || _)) { reg := bytes.asUInt }
-    bytes.zipWithIndex.map { case (b, i) => RegField(8, b,
-      RegWriteFn((valid, data) => {
+    when (valids.reduce(_ || _)) { reg := newBytes.asUInt }
+    Seq.tabulate(numBytes) { i =>
+      RegField(8, oldBytes(i),
+        RegWriteFn((valid, data) => {
         valids(i) := valid
-        when (valid) { bytes(i) := data }
+        when (valid) { newBytes(i) := data }
         Bool(true)
       }))}}