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Revert "switch back to Chisel2 for verilog build for now"

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This reverts commit 3673365b08.
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Howard Mao
2016-03-30 19:00:38 -07:00
parent 8e601f26e1
commit e77900f540
1 changed files with 1 additions and 1 deletions
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.travis.yml
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@@ -64,7 +64,7 @@ before_install:
- export CXX=g++-4.8 CC=gcc-4.8 - export CXX=g++-4.8 CC=gcc-4.8
script: script:
- make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make vsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default CHISEL_VERSION=3
- make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make fsim-verilog -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make emulator-ndebug -C regression CONFIG=$CONFIG TORTURE_CONFIG=default
- make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default - make emulator-asm-tests -C regression CONFIG=$CONFIG TORTURE_CONFIG=default