riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

New machine-mode timer facility

Browse Source 
Mirroring Andrew's commit to reference-chip
This commit is contained in:
Yunsup Lee 2015-07-07 17:26:07 -07:00
parent 4fbb0f80ff
commit e6a13cdeba
5 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefrag
View File

@ -162,7 +162,6 @@ asm_p_tests = \
rv64si-p-ma_addr \
rv64si-p-scall \
rv64si-p-sbreak \
rv64si-p-timer \
rv64ui-pm-lrsc \
rv64mi-p-csr \
rv64mi-p-mcsr \

2
riscv-tools

@ -1 +1 @@
Subproject commit 8a16e3481018623bc954caeba67e2f532db5f9a9
Subproject commit 7e8f1644187b91d7a6d79929e41fc50e2804fa97

2
rocket

@ -1 +1 @@
Subproject commit 4ad41b4b63ac14989b70bffb651491737bb0d4e8
Subproject commit d819fb28c3370747475d7c5f4b641723cab1fd0c

1
src/main/scala/PublicConfigs.scala
View File

@ -98,6 +98,7 @@ class DefaultConfig extends ChiselConfig (
case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
case NCustomMRWCSRs => 0
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLNManagers) + site(TLNClients)
case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)

2
uncore

@ -1 +1 @@
Subproject commit bf608ce9144d54f372f81f237ed25f5418337f14
Subproject commit 1894adb89da89f455110c35d7359ae89a8823890