diff --git a/Makefrag b/Makefrag
index 4ce1ab76..076aacd2 100644
--- a/Makefrag
+++ b/Makefrag
@@ -162,7 +162,6 @@ asm_p_tests = \
 	rv64si-p-ma_addr \
 	rv64si-p-scall \
 	rv64si-p-sbreak \
-	rv64si-p-timer \
 	rv64ui-pm-lrsc \
 	rv64mi-p-csr \
 	rv64mi-p-mcsr \
diff --git a/riscv-tools b/riscv-tools
index 8a16e348..7e8f1644 160000
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 8a16e3481018623bc954caeba67e2f532db5f9a9
+Subproject commit 7e8f1644187b91d7a6d79929e41fc50e2804fa97
diff --git a/rocket b/rocket
index 4ad41b4b..d819fb28 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 4ad41b4b63ac14989b70bffb651491737bb0d4e8
+Subproject commit d819fb28c3370747475d7c5f4b641723cab1fd0c
diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala
index 2b30f2c1..83b0a0f2 100644
--- a/src/main/scala/PublicConfigs.scala
+++ b/src/main/scala/PublicConfigs.scala
@@ -98,6 +98,7 @@ class DefaultConfig extends ChiselConfig (
       case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
       case NCustomMRWCSRs => 0
       //Uncore Paramters
+      case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
       case LNEndpoints => site(TLNManagers) + site(TLNClients)
       case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
       case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
diff --git a/uncore b/uncore
index bf608ce9..1894adb8 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit bf608ce9144d54f372f81f237ed25f5418337f14
+Subproject commit 1894adb89da89f455110c35d7359ae89a8823890