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New machine-mode timer facility

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Mirroring Andrew's commit to reference-chip
This commit is contained in:
Yunsup Lee
2015-07-07 17:26:07 -07:00
parent 4fbb0f80ff
commit e6a13cdeba
5 changed files with 4 additions and 4 deletions
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src/main/scala/PublicConfigs.scala
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@@ -98,6 +98,7 @@ class DefaultConfig extends ChiselConfig (
case CoreDCacheReqTagBits => 7 + log2Up(here(NDCachePorts))
case NCustomMRWCSRs => 0
//Uncore Paramters
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case LNEndpoints => site(TLNManagers) + site(TLNClients)
case LNHeaderBits => log2Ceil(site(TLNManagers)) + log2Up(site(TLNClients))
case TLBlockAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)