riscv/rocket-chip
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Debug regressions: use a plusarg to enable remote bitbang.

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This commit is contained in:
Megan Wachs
2017-12-19 17:13:08 -08:00
parent b643f3dca6
commit e6661a6982
4 changed files with 8 additions and 8 deletions
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2
src/main/scala/devices/debug/Periphery.scala
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@ -130,7 +130,7 @@ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam
io.clock := tbclock
io.reset := tbreset
io.enable := ~tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := ~tbreset
// Success is determined by the gdbserver