diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index f9e9e8c2..c9d42e8c 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -220,9 +220,6 @@ done_processing:
   jtag = new remote_bitbang_t(0);
   dtm = new dtm_t(htif_argc, htif_argv);
 
-  jtag = new remote_bitbang_t(0);
-  dtm = new dtm_t(to_dtm);
-
   signal(SIGTERM, handle_sigterm);
 
   bool dump;
diff --git a/csrc/remote_bitbang.cc b/csrc/remote_bitbang.cc
index c6fafa7c..07dc6e01 100644
--- a/csrc/remote_bitbang.cc
+++ b/csrc/remote_bitbang.cc
@@ -69,6 +69,7 @@ remote_bitbang_t::remote_bitbang_t(uint16_t port) :
   trstn = 1;
   quit = 0;
 
+  printf ("This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.\n");
   printf("Listening on port %d\n",
          ntohs(addr.sin_port));
   fflush(stdout);
diff --git a/regression/Makefile b/regression/Makefile
index 95e7af8f..76411e18 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -231,6 +231,8 @@ ifdef SEED
 SEED_ARG = --seed $(SEED)
 endif
 
+JTAG_DTM_SIM_ARGS = +verbose +jtag_rbb_enable=1 $(SEED_ARG)
+
 stamps/riscv-tests.stamp:
 	git -C $(abspath $(TOP)) submodule update --init riscv-tools
 	git -C $(abspath $(TOP))/riscv-tools submodule update --init --recursive riscv-tests
@@ -238,7 +240,7 @@ stamps/riscv-tests.stamp:
 
 stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
 	RISCV=$(RISCV) $(GDBSERVER) \
-	--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(VSIM_JTAG_VCDPLUS_32)" \
+	--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(VSIM_JTAG_VCDPLUS_32)" \
 	--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
 	-s $(RISCV)/share/openocd/scripts" \
 	--32 \
@@ -248,7 +250,7 @@ stamps/%/vsim-jtag-dtm-32-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
 
 stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
 	RISCV=$(RISCV) $(GDBSERVER) \
-	--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(VSIM_JTAG_VCDPLUS_64)" \
+	--sim_cmd="$(abspath $(TOP))/vsim/simv-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(VSIM_JTAG_VCDPLUS_64)" \
 	--server_cmd="$(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/bin/openocd $(OPENOCD_DEBUG) \
 	-s $(OPENOCD_INSTALL)_$(OPENOCD_VERSION)/share/openocd/scripts" \
 	--64 \
@@ -258,7 +260,7 @@ stamps/%/vsim-jtag-dtm-64-$(JTAG_DTM_TEST).stamp: stamps/%/vsim$(JTAG_STAMP_SUFF
 
 stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp:  stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
 	RISCV=$(RISCV) $(GDBSERVER) \
-	--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_32) dummybin" \
+	--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(EMULATOR_JTAG_VCDPLUS_32) dummybin" \
 	--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
 	-s $(RISCV)/share/openocd/scripts" \
 	--32 \
@@ -268,7 +270,7 @@ stamps/%/emulator-jtag-dtm-32-$(JTAG_DTM_TEST).stamp:  stamps/%/emulator$(JTAG_S
 
 stamps/%/emulator-jtag-dtm-64-$(JTAG_DTM_TEST).stamp:  stamps/%/emulator$(JTAG_STAMP_SUFFIX).stamp stamps/riscv-tests.stamp
 	RISCV=$(RISCV) $(GDBSERVER) \
-	--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) +verbose $(SEED_ARG) $(EMULATOR_JTAG_VCDPLUS_64) dummybin" \
+	--sim_cmd="$(abspath $(TOP))/emulator/emulator-$(PROJECT)-$*$(JTAG_DEBUG_SUFFIX) $(JTAG_DTM_SIM_ARGS) $(EMULATOR_JTAG_VCDPLUS_64) dummybin" \
 	--server_cmd="$(RISCV)/bin/openocd $(OPENOCD_DEBUG) \
 	-s $(RISCV)/share/openocd/scripts" \
 	--64 \
diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala
index 17c10e2d..3cec79e2 100644
--- a/src/main/scala/devices/debug/Periphery.scala
+++ b/src/main/scala/devices/debug/Periphery.scala
@@ -130,7 +130,7 @@ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam
     io.clock := tbclock
     io.reset := tbreset
 
-    io.enable    := ~tbreset
+    io.enable    := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
     io.init_done := ~tbreset
 
     // Success is determined by the gdbserver