riscv/rocket-chip
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Use correct kind of TileLink arbiter

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It was "correct" before, but broke Chisel3 build.
This commit is contained in:
Andrew Waterman 2016-03-28 22:53:47 -07:00
parent 5ce3527b88
commit e652821962
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/tile.scala
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@ -114,7 +114,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
uncachedPorts ++= roccs.flatMap(_.io.utl) uncachedPorts ++= roccs.flatMap(_.io.utl)
} }
val uncachedArb = Module(new ClientTileLinkIOArbiter(uncachedArbPorts.size)) val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size))
uncachedArb.io.in <> uncachedArbPorts uncachedArb.io.in <> uncachedArbPorts
uncachedArb.io.out +=: uncachedPorts uncachedArb.io.out +=: uncachedPorts