From e652821962d1876678618363e7899b0684c42ae2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 28 Mar 2016 22:53:47 -0700 Subject: [PATCH] Use correct kind of TileLink arbiter It was "correct" before, but broke Chisel3 build. --- rocket/src/main/scala/tile.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index f417c853..68c0714d 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -114,7 +114,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile( uncachedPorts ++= roccs.flatMap(_.io.utl) } - val uncachedArb = Module(new ClientTileLinkIOArbiter(uncachedArbPorts.size)) + val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size)) uncachedArb.io.in <> uncachedArbPorts uncachedArb.io.out +=: uncachedPorts