riscv/rocket-chip
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Abstract class for coherence policies

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This commit is contained in:
Henry Cook 2012-02-16 12:59:38 -08:00
parent d46e59a16d
commit e555fd3fc4
1 changed files with 22 additions and 17 deletions
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37
rocket/src/main/scala/coherence.scala
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@ -47,9 +47,7 @@ class ioTileLink extends Bundle {
val xact_finish = new TransactionFinish().asOutput val xact_finish = new TransactionFinish().asOutput
} }
trait ThreeStateIncoherence { trait CoherencePolicy {
val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
def cpuCmdToRW( cmd: Bits): (Bool, Bool) = { def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
val store = (cmd === M_XWR) val store = (cmd === M_XWR)
val load = (cmd === M_XRD) val load = (cmd === M_XRD)
@ -58,6 +56,10 @@ trait ThreeStateIncoherence {
val write = store || amo || (cmd === M_PFW) val write = store || amo || (cmd === M_PFW)
(read, write) (read, write)
} }
}
trait ThreeStateIncoherence extends CoherencePolicy {
val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
def isHit ( cmd: Bits, state: UFix): Bool = { def isHit ( cmd: Bits, state: UFix): Bool = {
val (read, write) = cpuCmdToRW(cmd) val (read, write) = cpuCmdToRW(cmd)
@ -87,32 +89,35 @@ trait ThreeStateIncoherence {
} }
trait FourStateCoherence { trait FourStateCoherence extends CoherencePolicy {
val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() } val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() } val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() } val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
def isHit ( cmd: Bits, state: UFix): Bool = { def isHit ( cmd: Bits, state: UFix): Bool = {
val is_hit = Bool(false) val (read, write) = cpuCmdToRW(cmd)
switch(cmd) { ((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
is(M_XRD) { (write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
is_hit := state === tileShared ||
state === tileExclusiveClean ||
state === tileExclusiveDirty
} }
is(M_XWR) {
is_hit := state === tileExclusiveClean || def isValid (state: UFix): Bool = {
state === tileExclusiveDirty state != tileInvalid
}
}
is_hit
} }
def needsWriteback (state: UFix): Bool = { def needsWriteback (state: UFix): Bool = {
state === tileExclusiveDirty state === tileExclusiveDirty
} }
def newStateOnWriteback() = tileInvalid
def newStateOnFlush() = tileInvalid
// TODO: New funcs as compared to incoherent protocol:
def newState(cmd: Bits, state: UFix): UFix
def newStateOnHit(cmd: Bits, state: UFix): UFix
def newStateOnPrimaryMiss(cmd: Bits): UFix
def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool
def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = { def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {