From e555fd3fc4b3f89b9e62ce3e48db4df3b3a525cd Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@s144.Millennium.Berkeley.EDU>
Date: Thu, 16 Feb 2012 12:59:38 -0800
Subject: [PATCH] Abstract class for coherence policies

---
 rocket/src/main/scala/coherence.scala | 39 +++++++++++++++------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala
index 7419555e..b55ac9a1 100644
--- a/rocket/src/main/scala/coherence.scala
+++ b/rocket/src/main/scala/coherence.scala
@@ -47,9 +47,7 @@ class ioTileLink extends Bundle {
   val xact_finish = new TransactionFinish().asOutput
 }
 
-trait ThreeStateIncoherence {
-  val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
-
+trait CoherencePolicy {
   def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
     val store   = (cmd === M_XWR)
     val load    = (cmd === M_XRD)
@@ -58,6 +56,10 @@ trait ThreeStateIncoherence {
     val write   = store || amo || (cmd === M_PFW)
     (read, write)
   }
+}
+
+trait ThreeStateIncoherence extends CoherencePolicy {
+  val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }
 
   def isHit ( cmd: Bits, state: UFix): Bool = {
     val (read, write) = cpuCmdToRW(cmd)
@@ -87,32 +89,35 @@ trait ThreeStateIncoherence {
 
 }
 
-trait FourStateCoherence {
+trait FourStateCoherence extends CoherencePolicy {
 
   val tileInvalid :: tileShared :: tileExclusiveClean :: tileExclusiveDirty :: Nil = Enum(4){ UFix() }
   val globalInvalid :: globalShared :: globalExclusiveClean :: Nil = Enum(3){ UFix() }
   val probeInvalidate :: probeDowngrade :: probeCopy :: Nil = Enum(3){ UFix() }
 
   def isHit ( cmd: Bits, state: UFix): Bool = {
-    val is_hit = Bool(false)
-    switch(cmd) {
-      is(M_XRD) {
-        is_hit := state === tileShared || 
-                  state === tileExclusiveClean ||
-                  state === tileExclusiveDirty
-      }
-      is(M_XWR) {
-        is_hit := state === tileExclusiveClean ||
-                  state === tileExclusiveDirty
-      }
-    }
-    is_hit
+    val (read, write) = cpuCmdToRW(cmd)
+    ((read && ( state === tileShared || state === tileExclusiveClean || state === tileExclusiveDirty)) ||
+     (write && (state === tileExclusiveClean || state === tileExclusiveDirty)))
+  }
+
+  def isValid (state: UFix): Bool = {
+    state != tileInvalid
   }
 
   def needsWriteback (state: UFix): Bool = {
     state === tileExclusiveDirty
   }
 
+  def newStateOnWriteback() = tileInvalid
+  def newStateOnFlush() = tileInvalid
+
+  // TODO: New funcs as compared to incoherent protocol:
+  def newState(cmd: Bits, state: UFix): UFix
+  def newStateOnHit(cmd: Bits, state: UFix): UFix 
+  def newStateOnPrimaryMiss(cmd: Bits): UFix 
+  def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix 
+
   def needsSecondaryXact (cmd: Bits, outstanding: TransactionInit): Bool
 
   def getMetaUpdateOnProbe (incoming: ProbeRequest): Bits = {