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Chisel3 compat: merge NASTIMasterIO and NASTISlaveIO so we do not depend on flip() modifying the object

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This commit is contained in:
Howard Mao 2015-09-24 16:57:50 -07:00
parent ee65f6a84d
commit e3d2207c72
2 changed files with 14 additions and 16 deletions
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26
junctions/src/main/scala/nasti.scala
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@ -55,7 +55,7 @@ trait NASTIChannel extends NASTIBundle
trait NASTIMasterToSlaveChannel extends NASTIChannel
trait NASTISlaveToMasterChannel extends NASTIChannel
class NASTIMasterIO extends Bundle {
class NASTIIO extends Bundle {
val aw = Decoupled(new NASTIWriteAddressChannel)
val w = Decoupled(new NASTIWriteDataChannel)
val b = Decoupled(new NASTIWriteResponseChannel).flip
@ -63,8 +63,6 @@ class NASTIMasterIO extends Bundle {
val r = Decoupled(new NASTIReadDataChannel).flip
}
class NASTISlaveIO extends NASTIMasterIO { flip() }
trait HasNASTIMetadata extends NASTIBundle {
val addr = UInt(width = nastiXAddrBits)
val len = UInt(width = nastiXLenBits)
@ -182,9 +180,9 @@ object NASTIWriteResponseChannel {
}
}
class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NASTIParameters {
class MemIONASTIIOConverter(cacheBlockOffsetBits: Int) extends MIFModule with NASTIParameters {
val io = new Bundle {
val nasti = new NASTISlaveIO
val nasti = (new NASTIIO).flip
val mem = new MemIO
}
@ -238,8 +236,8 @@ class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule wi
/** Arbitrate among arbN masters requesting to a single slave */
class NASTIArbiter(val arbN: Int) extends NASTIModule {
val io = new Bundle {
val master = Vec(new NASTISlaveIO, arbN)
val slave = new NASTIMasterIO
val master = Vec(new NASTIIO, arbN).flip
val slave = new NASTIIO
}
if (arbN > 1) {
@ -346,7 +344,7 @@ class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
/** A slave that send decode error for every request it receives */
class NASTIErrorSlave extends NASTIModule {
val io = new NASTISlaveIO
val io = (new NASTIIO).flip
when (io.ar.fire()) { printf("Invalid read address %x\n", io.ar.bits.addr) }
when (io.aw.fire()) { printf("Invalid write address %x\n", io.aw.bits.addr) }
@ -401,8 +399,8 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
val nSlaves = addrmap.size
val io = new Bundle {
val master = new NASTISlaveIO
val slave = Vec(new NASTIMasterIO, nSlaves)
val master = (new NASTIIO).flip
val slave = Vec(new NASTIIO, nSlaves)
}
var ar_ready = Bool(false)
@ -479,8 +477,8 @@ class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
extends NASTIModule {
val io = new Bundle {
val masters = Vec(new NASTISlaveIO, nMasters)
val slaves = Vec(new NASTIMasterIO, nSlaves)
val masters = Vec(new NASTIIO, nMasters).flip
val slaves = Vec(new NASTIIO, nSlaves)
}
val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io }
@ -594,8 +592,8 @@ case object NASTIAddrHashMap extends Field[AddrHashMap]
class NASTIInterconnectIO(val nMasters: Int, val nSlaves: Int) extends Bundle {
/* This is a bit confusing. The interconnect is a slave to the masters and
* a master to the slaves. Hence why the declarations seem to be backwards. */
val masters = Vec(new NASTISlaveIO, nMasters)
val slaves = Vec(new NASTIMasterIO, nSlaves)
val masters = Vec(new NASTIIO, nMasters).flip
val slaves = Vec(new NASTIIO, nSlaves)
override def cloneType =
new NASTIInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
}

4
junctions/src/main/scala/smi.scala
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@ -250,10 +250,10 @@ class SMIIONASTIWriteIOConverter(val dataWidth: Int, val addrWidth: Int)
}
/** Convert NASTI protocol to SMI protocol */
class SMIIONASTISlaveIOConverter(val dataWidth: Int, val addrWidth: Int)
class SMIIONASTIIOConverter(val dataWidth: Int, val addrWidth: Int)
extends NASTIModule {
val io = new Bundle {
val nasti = new NASTISlaveIO
val nasti = (new NASTIIO).flip
val smi = new SMIIO(dataWidth, addrWidth)
}