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tilelink2: ensure RegFields don't exceed their bounds

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This commit is contained in:
Wesley W. Terpstra 2016-09-02 23:01:15 -07:00
parent 8343070639
commit e3b3543841
1 changed files with 2 additions and 2 deletions
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src/main/scala/uncore/tilelink2/RegMapper.scala
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@ -92,7 +92,7 @@ object RegMapper
val womask = backMask(high, low).andR() val womask = backMask(high, low).andR()
val data = if (field.write.combinational) back.bits.data else front.bits.data val data = if (field.write.combinational) back.bits.data else front.bits.data
val (f_riready, f_rovalid, f_data) = field.read.fn(rivalid(i) && rimask, roready(i) && romask) val (f_riready, f_rovalid, f_data) = field.read.fn(rivalid(i) && rimask, roready(i) && romask)
val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data) val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data(high, low))
riready(i) := f_riready || !rimask riready(i) := f_riready || !rimask
wiready(i) := f_wiready || !wimask wiready(i) := f_wiready || !wimask
rovalid(i) := f_rovalid || !romask rovalid(i) := f_rovalid || !romask
@ -101,7 +101,7 @@ object RegMapper
wifire(reg) = wiready(i) +: wifire(reg) wifire(reg) = wiready(i) +: wifire(reg)
rofire(reg) = rovalid(i) +: rofire(reg) rofire(reg) = rovalid(i) +: rofire(reg)
wofire(reg) = wovalid(i) +: wofire(reg) wofire(reg) = wovalid(i) +: wofire(reg)
dataOut(reg) = dataOut(reg) | (f_data << low) dataOut(reg) = dataOut(reg) | ((f_data << low) & (~UInt(0, width = high+1)))
} }
// Is the selected register ready? // Is the selected register ready?