From e3b35438419e4a5ce76d72422d80935009bea1e9 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 2 Sep 2016 23:01:15 -0700 Subject: [PATCH] tilelink2: ensure RegFields don't exceed their bounds --- src/main/scala/uncore/tilelink2/RegMapper.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegMapper.scala b/src/main/scala/uncore/tilelink2/RegMapper.scala index 033d507b..f7e34e5d 100644 --- a/src/main/scala/uncore/tilelink2/RegMapper.scala +++ b/src/main/scala/uncore/tilelink2/RegMapper.scala @@ -92,7 +92,7 @@ object RegMapper val womask = backMask(high, low).andR() val data = if (field.write.combinational) back.bits.data else front.bits.data val (f_riready, f_rovalid, f_data) = field.read.fn(rivalid(i) && rimask, roready(i) && romask) - val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data) + val (f_wiready, f_wovalid) = field.write.fn(wivalid(i) && wimask, woready(i) && womask, data(high, low)) riready(i) := f_riready || !rimask wiready(i) := f_wiready || !wimask rovalid(i) := f_rovalid || !romask @@ -101,7 +101,7 @@ object RegMapper wifire(reg) = wiready(i) +: wifire(reg) rofire(reg) = rovalid(i) +: rofire(reg) wofire(reg) = wovalid(i) +: wofire(reg) - dataOut(reg) = dataOut(reg) | (f_data << low) + dataOut(reg) = dataOut(reg) | ((f_data << low) & (~UInt(0, width = high+1))) } // Is the selected register ready?