riscv/rocket-chip
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fix control bug in LLC

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structural hazard on tag ram caused deadlock
This commit is contained in:
Andrew Waterman 2012-08-03 18:59:37 -07:00
parent def913096e
commit e3726c4db0
1 changed files with 2 additions and 1 deletions
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3
rocket/src/main/scala/llc.scala
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@ -154,13 +154,14 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Component
val conflicts = Cat(Bits(0), (0 until outstanding).map(i => valid(i) && io.cpu.bits.addr(log2Up(sets)-1, 0) === mshr(i).addr(log2Up(sets)-1, 0)):_*) val conflicts = Cat(Bits(0), (0 until outstanding).map(i => valid(i) && io.cpu.bits.addr(log2Up(sets)-1, 0) === mshr(i).addr(log2Up(sets)-1, 0)):_*)
io.cpu.ready := !conflicts.orR && !validBits.andR io.cpu.ready := !conflicts.orR && !validBits.andR
io.data.valid := replay && io.tag.ready || writeback io.data.valid := writeback
io.data.bits.rw := Bool(false) io.data.bits.rw := Bool(false)
io.data.bits.tag := mshr(replayId).tag io.data.bits.tag := mshr(replayId).tag
io.data.bits.isWriteback := Bool(true) io.data.bits.isWriteback := Bool(true)
io.data.bits.addr := Cat(mshr(writebackId).old_tag, mshr(writebackId).addr(log2Up(sets)-1, 0)).toUFix io.data.bits.addr := Cat(mshr(writebackId).old_tag, mshr(writebackId).addr(log2Up(sets)-1, 0)).toUFix
io.data.bits.way := mshr(writebackId).way io.data.bits.way := mshr(writebackId).way
when (replay) { when (replay) {
io.data.valid := io.tag.ready
io.data.bits.isWriteback := Bool(false) io.data.bits.isWriteback := Bool(false)
io.data.bits.addr := mshr(replayId).addr io.data.bits.addr := mshr(replayId).addr
io.data.bits.way := mshr(replayId).way io.data.bits.way := mshr(replayId).way