From e3391b36b2768584bee7092014357f80fc264716 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 21 Jun 2016 10:43:44 -0700 Subject: [PATCH] get rid of MuxBundle now that MuxCase and MuxLookup are fixed --- uncore/src/main/scala/coherence.scala | 10 +++++----- uncore/src/main/scala/converters.scala | 8 ++++---- uncore/src/main/scala/dma.scala | 2 +- uncore/src/main/scala/util.scala | 10 ---------- 4 files changed, 10 insertions(+), 20 deletions(-) diff --git a/uncore/src/main/scala/coherence.scala b/uncore/src/main/scala/coherence.scala index f7eb5992..3bf224e9 100644 --- a/uncore/src/main/scala/coherence.scala +++ b/uncore/src/main/scala/coherence.scala @@ -197,7 +197,7 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) { def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = { val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) - MuxBundle(meta, Array( + MuxCase(meta, Array( incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateAck) -> popped)) } @@ -299,7 +299,7 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) { def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = { val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) - MuxBundle(meta, Array( + MuxCase(meta, Array( incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateAck) -> popped)) } @@ -417,7 +417,7 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) { def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = { val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) - MuxBundle(meta, Array( + MuxCase(meta, Array( incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateAck) -> popped)) } @@ -537,7 +537,7 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) { def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = { val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) - MuxBundle(meta, Array( + MuxCase(meta, Array( incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateAck) -> popped)) } @@ -680,7 +680,7 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d def managerMetadataOnRelease(incoming: HasReleaseType, src: UInt, meta: ManagerMetadata) = { val popped = ManagerMetadata(sharers=dir.pop(meta.sharers, src))(meta.p) - MuxBundle(meta, Array( + MuxCase(meta, Array( incoming.is(releaseInvalidateData) -> popped, incoming.is(releaseInvalidateAck) -> popped, incoming.is(releaseInvalidateDataMigratory) -> popped, diff --git a/uncore/src/main/scala/converters.scala b/uncore/src/main/scala/converters.scala index 9be72d61..93b1372c 100644 --- a/uncore/src/main/scala/converters.scala +++ b/uncore/src/main/scala/converters.scala @@ -887,7 +887,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String) wmask = put_wmask.toBits) io.out.acquire.valid := sending_put || (!shrink && io.in.acquire.valid) - io.out.acquire.bits := MuxBundle(get_block_acquire, Seq( + io.out.acquire.bits := MuxCase(get_block_acquire, Seq( sending_put -> put_block_acquire, smallget -> get_acquire, smallput -> put_acquire)) @@ -961,7 +961,7 @@ class TileLinkIOWidener(innerTLId: String, outerTLId: String) data = ognt.data) io.in.grant.valid := returning_data || (!stretch && io.out.grant.valid) - io.in.grant.bits := MuxBundle(default_grant, Seq( + io.in.grant.bits := MuxCase(default_grant, Seq( returning_data -> get_block_grant, smallgnt -> get_grant)) io.out.grant.ready := !returning_data && (stretch || io.in.grant.ready) @@ -1085,7 +1085,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String) val pass_valid = io.in.acquire.valid && !stretch - io.out.acquire.bits := MuxBundle(Wire(io.out.acquire.bits, init=iacq), Seq( + io.out.acquire.bits := MuxCase(Wire(io.out.acquire.bits, init=iacq), Seq( (sending_put, put_block_acquire), (shrink, get_block_acquire), (smallput, put_acquire), @@ -1138,7 +1138,7 @@ class TileLinkIONarrower(innerTLId: String, outerTLId: String) io.in.grant.valid := sending_get || (io.out.grant.valid && !ognt_block) io.out.grant.ready := !sending_get && (ognt_block || io.in.grant.ready) - io.in.grant.bits := MuxBundle(Wire(io.in.grant.bits, init=ognt), Seq( + io.in.grant.bits := MuxCase(Wire(io.in.grant.bits, init=ognt), Seq( sending_get -> get_block_grant, smallget_grant -> get_grant)) diff --git a/uncore/src/main/scala/dma.scala b/uncore/src/main/scala/dma.scala index 16fa01b0..79c88be3 100644 --- a/uncore/src/main/scala/dma.scala +++ b/uncore/src/main/scala/dma.scala @@ -369,7 +369,7 @@ class DmaTracker(implicit p: Parameters) extends DmaModule()(p) io.mem.acquire.valid := (state === s_get) || (state === s_put && get_done) || (state === s_prefetch && !prefetch_busy(prefetch_id)) - io.mem.acquire.bits := MuxBundle( + io.mem.acquire.bits := MuxLookup( state, prefetch_acquire, Seq( s_get -> get_acquire, s_put -> put_acquire)) diff --git a/uncore/src/main/scala/util.scala b/uncore/src/main/scala/util.scala index d0afa758..b6d11fd5 100644 --- a/uncore/src/main/scala/util.scala +++ b/uncore/src/main/scala/util.scala @@ -4,16 +4,6 @@ package uncore import Chisel._ -object MuxBundle { - def apply[T <: Data] (default: T, mapping: Seq[(Bool, T)]): T = { - mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b)) - } - - def apply[T <: Data] (key: UInt, default: T, mapping: Seq[(UInt, T)]): T = { - apply(default, mapping.map{ case (a, b) => (a === key, b) }) - } -} - // Produces 0-width value when counting to 1 class ZCounter(val n: Int) { val value = Reg(init=UInt(0, log2Ceil(n)))