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Fix errors in derived cache params

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This commit is contained in:
Henry Cook 2014-08-12 14:55:44 -07:00
parent 9ab3a4262c
commit e26f8a6f6a
1 changed files with 6 additions and 5 deletions
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11
uncore/src/main/scala/cache.scala
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@ -13,18 +13,19 @@ abstract trait CacheParameters extends UsesParameters {
val vaddrBits = params(VAddrBits) val vaddrBits = params(VAddrBits)
val pgIdxBits = params(PgIdxBits) val pgIdxBits = params(PgIdxBits)
val nSets = params(NSets) val nSets = params(NSets)
val nWays = params(NWays)
val blockOffBits = params(BlockOffBits) val blockOffBits = params(BlockOffBits)
val wordBits = params(WordBits)
val rowBits = params(RowBits)
val wordOffBits = log2Up(wordBits)
val idxBits = log2Up(nSets) val idxBits = log2Up(nSets)
val untagBits = blockOffBits + idxBits val untagBits = blockOffBits + idxBits
val tagBits = paddrBits - untagBits val tagBits = paddrBits - untagBits
val nWays = params(NWays)
val wayBits = log2Up(nWays) val wayBits = log2Up(nWays)
val isDM = nWays == 1 val isDM = nWays == 1
val wordBits = params(WordBits)
val wordBytes = wordBits/8
val wordOffBits = log2Up(wordBytes)
val rowBits = params(RowBits)
val rowWords = rowBits/wordBits val rowWords = rowBits/wordBits
val rowBytes = rowBits*8 val rowBytes = rowBits/8
val rowOffBits = log2Up(rowBytes) val rowOffBits = log2Up(rowBytes)
val refillCycles = params(TLDataBits)/rowBits val refillCycles = params(TLDataBits)/rowBits
} }