From e26f8a6f6ae8c1da134939a9c4177752f34a5a3c Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 12 Aug 2014 14:55:44 -0700
Subject: [PATCH] Fix errors in derived cache params

---
 uncore/src/main/scala/cache.scala | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala
index 21cf582e..d52e692a 100644
--- a/uncore/src/main/scala/cache.scala
+++ b/uncore/src/main/scala/cache.scala
@@ -13,18 +13,19 @@ abstract trait CacheParameters extends UsesParameters {
   val vaddrBits = params(VAddrBits)
   val pgIdxBits = params(PgIdxBits) 
   val nSets = params(NSets)
-  val nWays = params(NWays)
   val blockOffBits = params(BlockOffBits)
-  val wordBits = params(WordBits)
-  val rowBits = params(RowBits)
-  val wordOffBits = log2Up(wordBits)
   val idxBits = log2Up(nSets)
   val untagBits = blockOffBits + idxBits
   val tagBits = paddrBits - untagBits
+  val nWays = params(NWays)
   val wayBits = log2Up(nWays)
   val isDM = nWays == 1
+  val wordBits = params(WordBits)
+  val wordBytes = wordBits/8
+  val wordOffBits = log2Up(wordBytes)
+  val rowBits = params(RowBits)
   val rowWords = rowBits/wordBits 
-  val rowBytes = rowBits*8
+  val rowBytes = rowBits/8
   val rowOffBits = log2Up(rowBytes)
   val refillCycles = params(TLDataBits)/rowBits
 }