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[commitlog] CSR's cycle optionally set to instret

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- Allows debugging Rocket against Spike by having timer interrupts
    occur in the same place in the instruction stream for both.
This commit is contained in:
Christopher Celio 2015-09-11 23:08:23 -07:00
parent 7d14abf262
commit e22bf02a80
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/csr.scala
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@ -123,8 +123,8 @@ class CSRFile extends CoreModule
val reg_fromhost = Reg(init=Bits(0, xLen)) val reg_fromhost = Reg(init=Bits(0, xLen))
val reg_stats = Reg(init=Bool(false)) val reg_stats = Reg(init=Bool(false))
val reg_time = Reg(UInt(width = xLen)) val reg_time = Reg(UInt(width = xLen))
val reg_cycle = WideCounter(xLen)
val reg_instret = WideCounter(xLen, io.retire) val reg_instret = WideCounter(xLen, io.retire)
val reg_cycle = if (EnableCommitLog) { reg_instret } else { WideCounter(xLen) }
val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _)) val reg_uarch_counters = io.uarch_counters.map(WideCounter(xLen, _))
val reg_fflags = Reg(UInt(width = 5)) val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3)) val reg_frm = Reg(UInt(width = 3))