riscv/rocket-chip
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update to newest rocket

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Andrew Waterman committed 2012-11-25 04:40:46 -08:00
1 parent 9372912a9c
commit e12af07722
4 files changed
+6 -6
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src/main/scala/RocketChip.scala
+2 -2
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@@ -207,8 +207,8 @@ class Top extends Component {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val ic = ICacheConfig(128, 2, co)
val dc = DCacheConfig(128, 4, co,
val ic = ICacheConfig(128, 2, co, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, co, ntlb = 8,
nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(NTILES, co, ic, dc,
fpu = true, vec = true)